rtl2gds

Here are 8 public repositories matching this topic...

The-OpenROAD-Project / OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

magic asic rtl verilog vlsi foundry yosys klayout caravel netgen system-on-chip openroad openram skywater 130nm soc-design rtl2gds

Updated Dec 22, 2024
Python

lakshmi-sathi / avsdpll_1v8

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8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.

asic ic intellectual-property pll analog-circuit rtl2gds clock-multiplier phase-detector charge-pump manufacturable

Updated Jul 31, 2021

AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop

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Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130

asic vlsi vlsi-physical-design rtl2gds openlane sky130 openlane-flow

Updated Sep 17, 2022

aasthadave9 / Advanced-Physical-Design-Using-OpenLANE-Sky130

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This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an opensource RTL2GDS flow using OpenLANE and opensource PDK provided by Google/SkyWater130

linux open-source asic hardware vlsi-physical-design openroad rtl2gds openlane sky130

Updated Jul 7, 2021

meeeeet / RTL-to-GDS-Implementation-of-SerDes

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verilog vlsi-physical-design openroad asic-design rtl2gds

Updated Feb 22, 2024
Verilog

aieask / vsd_pll

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8x PLL Clock Multiplier PLL Design with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving an 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.