Deep learning toolkit-enabled VLSI placement
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Dec 26, 2024 - C++
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vlsi-physical-design
Here are 64 public repositories matching this topic...
A High-performance Timing Analysis Tool for VLSI Systems
parallel-computing eda circuit-simulator cad verilog cpp17 circuit-simulation vlsi circuit-analysis computer-aided-design vlsi-physical-design sta electronic-design-automation vlsi-circuits static-timing-analysis
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May 26, 2023 - Verilog
Standard Cell Library based Memory Compiler using FF/Latch cells
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Jun 15, 2024 - Verilog
Dr. CU, VLSI Detailed Routing Tool Developed by CUHK
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Mar 20, 2023 - C++
A Standalone Structural Verilog Parser
flex eda verilog cpp17 circuit computer-aided-design vlsi-physical-design electronic-design-automation vlsi-circuits bison-yacc
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Mar 31, 2022 - Verilog
VLSI EDA Global Router
router eda vlsi vlsi-physical-design electronic-design-automation vlsi-circuits globalrouter ispd lattice-graph multi-maze-routing
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Jan 22, 2018 - C++
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
eda circuits cpp17 vlsi computer-aided-design vlsi-physical-design sta spef electronic-design-automation vlsi-circuits parasitic static-timing-analysis
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Aug 7, 2022 - C++
Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
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Sep 17, 2022
DATC RDF
routing eda cad vlsi logic-synthesis placement vlsi-physical-design design-automation design-flow vlsi-cad ieee-ceda ieee-ceda-datc vlsi-design-flow clock-tree
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Jul 31, 2020 - Verilog
Steiner Shallow-Light Tree for VLSI Routing
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Jul 11, 2024 - C++
Courseworks of CS6165 VLSI Physical Design Automation, NTHU.
eda vlsi nthu vlsi-physical-design vlsi-design vlsi-placement vlsi-cad physical-design-automation vlsi-floorplan vlsi-routing two-way-min-cut fixed-outline global-placement global-routing
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Jan 23, 2021 - C++
This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In this project, a PicoRV32a SoC is taken and then the RTL to GDSII Flow is implemented with Openlane using Skywater130nm PDK. Custom-designed standard cells with Sky130 PDK are also used in the flow. Timing Optimisa…
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Jul 9, 2021 - Verilog
This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK
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Feb 22, 2022
Some simple examples for the Magic VLSI physical chip layout tool.
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Mar 9, 2021
Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.
signal-processing fast-fourier-transform digital-signal-processing vlsi-physical-design fpga-accelerator vlsi-design vlsi-project
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May 20, 2020 - Verilog
A LEF/DEF Utility.
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Aug 15, 2019 - Prolog
Examples of the TCL Scripts for different purposes and for VLSI Physical Design are provided here for your reference
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Dec 30, 2022 - Tcl
5 Day TCL begginer to advanced training workshop by VSD
linux bash open-source csv workshop tcl synthesis yosys shell-scripting vlsi-physical-design hardware-description-language static-timing-analysis tcl-programming tcl-extensions tcl-procedures opentimer eda-tools
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Oct 18, 2023 - Verilog
VLSI CAD Algorithm Visualizations implemented as Java Applications
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Aug 23, 2023 - Java
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