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Achievement: Pull Sharkx2Achievement: Quickdraw

Achievements

Achievement: Pull Sharkx2Achievement: Quickdraw

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@Abhiyanta-Community

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meeeeet/README.md

Hi , I'm Meet Sangani

  • 👀 I’m interested in RTL Design and Design Verification.
  • 🌱 I’m currently learning Advanced Bus Protocols, Verification Methodologies and RISC-V Architecture.
  • 📫 How to reach me : [email protected]

meeeeet

meeeeet

Pinned Loading

  1. 5-Stage-Pipelined-RISC-V-Processor 5-Stage-Pipelined-RISC-V-Processor Public

    Verilog

  2. UVM-based-FPU-VIP UVM-based-FPU-VIP Public

    SystemVerilog 1

  3. RTL-to-GDS-Implementation-of-SerDes RTL-to-GDS-Implementation-of-SerDes Public

    Verilog 13 2

  4. Single-Cycle-MIPS32-Processor Single-Cycle-MIPS32-Processor Public

    Verilog 1