In this workshop, we will see what are all the steps involved in making an Application Specific Intergrated Circuit(ASIC) from RTL to GDSII.
The field we are exploring involves the chips inside boards such as the Arduino board and the VSDSquadron. The image below shows Arduino board.
The block diagram of the board, along with all its peripherals, can be found in the image below.
Since we are dealing with only the central chip, if we open it, it will reveal the package with connections to the chip inside.
Connections to and from the outside world occur through the I/O pads. The entire logic (netlist) is placed inside the core. The logic, along with the I/O pads, is referred to as the DIE.
The core is filled with various IPs and macros.
RISC-V is an instruction set architecture which is an interface between software(C, python, java programs) and hardware(Layout).
For a software program to run on hardware, it passes through many interfaces and applications, such as system software, which handles memory allocation and low-level system functions, as well as a compiler that converts the software code into assembly instructions, and an assembler that translates these assembly instructions into machine code.
The interface that implements the instruction set architecture is the RTL Verilog code. This RTL code is converted into a layout that executes the program.
OpenLane is a flow developed by efabless for opensource skywater sky130 PDK. Three major requirements for an ASIC design are
- RTL Designs
- EDA Tools
- PDK
RTL Designs describes the flow of data between registers and the operations performed on the data.
Electronic Design Automation tools help design and verify whether the RTL code meets the specifications and functionality of the system.
A Process Design Kit (PDK) serves as an interface between the designer and the foundry. It contains all the necessary information and files required by the designer to design integrated circuits for a specific fabrication process offered by the foundry. The PDK includes various files and data that enable effective communication and collaboration between the designer and the foundry. These files help the designer understand the foundry's process, design rules, and available components, allowing them to create designs that are optimized for the foundry's manufacturing capabilities.
The steps in the RTL to GDSII flow include
Synthesis: Synthesis is the process of converting RTL code into a netlist, which comprises standard cell libraries and their connections.
Opensource Tools used : yosys,ABC
Floorplan: This is the process of defining the layout of the ASIC, including the placement of standard cells, macros, and I/O pads. The height and width of the core are decided in this step. Ideally, the power distribution network is also established at this stage. In OpenLane, this occurs after CTS. All preplaced cells are located in the floor plan stage.
Placement: refers to the process of positioning standard cells in rows on the ASIC. This step is essential for ensuring that the design meets performance, area, and power requirements. Placement occurs in two stages: Global Placement and Detailed Placement.
Clock Tree Synthesis: After CTS, timing checks are performed to ensure setup and hold constraints are met. If timing is not met, previous steps like placement may need to be revisited and optimized.
Routing: Signal routing happens after clock routing in CTS stage. Routing is divided into Global routing and Detailed routing.
Signoff: There should not be any DRC or LVS errors for the design to converge.
docker
./flow.tcl -interactive
package require openlane
prep -design picorv32a
This step will create a folder in runs directory.
After run_synthesis command, it will generate a netlist file picorv32a.synthesis.v in the results synthesis folder.
Chip area of the module is obtained at the end of the synthesis. Flop ratio is calculated using the statistics obtained from the synthesis step.
Flop ratio = no.of Dff used / total no. of cells
Implementation of floorplan
run_floorplan
Utilization factor and aspect ratio can be assigned at this stage. If there are any macros, these pre-placed macros are positioned in this step. Decoupling capacitors and pin placements are also handled at this stage.
A .def file is generated at the end of the floorplan stage. The .def file can be viewed using the Magic tool.
Using the FP_IO_MODE switch set to 0 and 1, one mode sets the I/O pins equidistantly, while the other places them randomly.
Vertical and Horizontal pins are set using the switches FP_IO_VMETAL and FP_IO_HMETAL
Implementation of Placement
run_placement
Placement determines the arrangement of standard cells within the chip. It refers to the process of positioning standard cells, macros, and I/O pads on the ASIC layout.
Both floor planning and placement do not add any extra logic to the synthesized netlist.
In this case, Characterization of an inverter starts from the .mag file, not from scratch. From this inverter layout, a SPICE deck is generated, and then the characterization of the cell is performed. Characterization involves simulating the inverter's performance under various conditions using ngspice. We calculate Rise transition delay, Fall transition delay, rise cell delay, fall cell delay. Create a LEF file from the layout which can be used to include this cell in any larger design.
Opening the sky130_inv.mag file in magic
extracting spice from the mag file using the commands
extract all
ext2spice cthresh 0 rthresh 0
ext2spice
Generated sky130_inv.spice file
Make some changes to the spice desk by including Vdd, input voltage (pulse) and trans response
Running the modified spice file using ngspice
Plotting different values from the graph
Rise time: Time taken for the output waveform to transition from 20% to 80% of its maximum value.
x0 = 2.164 y0 = 0.659
x1 = 2.205 y1 = 2.639
rise time = x1 - x0 = 0.041ns
Fall time: Time taken for the output waveform to transition from 80% to 20% of its maximum value.
x0 = 4.040 y0 = 2.64
x1 = 4.068 y1 = 0.660
fall time = x1 - x0 = 0.028ns
Rise cell delay: The time taken for a 50% transition at the output (0 to 1) corresponding to a 50% transition at the input (1 to 0)
x0 = 2.186 y0 = 1.65
x1 = 2.151 y1 = 1.65
Propogation delay = 0.03ns
Fall cell delay : The time taken for a 50% transition at the output (1 to 0) corresponding to a 50% transition at the input (0 to 1)
x0 = 4.054 y0 = 1.65
x1 = 4.05 y1 = 1.65
propogation delay = 0.004ns
writing lef file sky130_INV_PA1.lef
To include the customized LEF file sy130_INV_PA1.lef into the picorv32a design, the config.tcl file must be updated. The LEF file and the corresponding libraries also need to be included in the config file.
set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
add_lefs -src $lefs
These commands need to be added to the flow to incorporate the custom inverter cell into the ASIC flow during synthesis.
The cell sky130_INV_PA1 has been used 1554 times in the synthesis.
During the synthesis, the chip area of the module is 147712.9184
tns = -711.59 wns = -23.89
By changing the SYNTH_STRATEGY from AREA to DELAY, the TNS and WNS values changed to zero, but this resulted in an increased chip area of 181730.544.
commands to change the swithces
set ::$env(SYNTH_STRATAGEY) "DELAY 3"
echo $::env(SYNTH_STRATAGEY) - To print the value
Similar switches to optimize the netlist at synthesis stage
SYNTH_MAX_FANOUT
SYNTH_SIZING
SYNTH_BUFFERING
SYNTH_DRIVING_CELL
Running floorplan by the following commands
init_floorplan
place_io
tap_decap_or
sky130_INV_PA1 cell in merged.lef file
pre_sta.conf configuration file along with my_base.sdc is used to do STA analysis
.def generated after run_placement & gen_pdn
run_routing
Routing occurs over many iterations. Below are the images showing that in the 4th iteration there are 21 violations, and in the 57th iteration, the design converges with zero violations.
Post-routing static timing analysis (STA) can be performed within the OpenFlow itself using openraod command which invokes OpenSTA.
read_lef /openLANE_flow/designs/picorv32a/src/22-08_08-41/tmp/merged.lef
read_def /openLANE_flow/designs/picorv32a/src/22-08_08-41/results/routing/picorv32a.def
write_db picorv32_rout.db
read_db picorv32_rout.db
read_verilog /openLANE_flow/designs/picorv32a/results/synthesis/picorv32a.synthesis_preroute.v
read_liberty $::env(LIB_SYNTH_COMPLETE)
link_design picorv32a
read_sdc /openLANE_flow/designs/picorv32a/src/my_base.sdc
set_propagated_clock [all_clocks]
read_spef /openLANE_flow/designs/picorv32a/src/22-08_08-41/results/routing/picorv32a.spef
report_checks -path_delay min_max -fields {slew trans net cap input_pin} -format clock_full_expanded -digits 4
To check all the rules regarding front end layers, implant layers check this documentation https://skywater-pdk.readthedocs.io/en/main/rules/periphery.html#poly
By making some changes in the tech file, we reducing the DRC errors.
