-
Notifications
You must be signed in to change notification settings - Fork 379
Issues: The-OpenROAD-Project/OpenLane
Magic DRC check reporting 0 errors in Openlane and MPW local ...
#2040
by ellen-wood
was closed Nov 11, 2023
Closed
2
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Author
Label
Projects
Milestones
Assignee
Sort
Issues list
Detailed routing failed: Signal 6 received Stack trace
bug
Something isn't working
OpenROAD
An issue with an OpenROAD component
waiting on op
Information has been requested from the Issue Author
#2168
opened Nov 18, 2024 by
Asma-Mohsin
Upgrade to rtl_macro_placer
OpenLane 2
Scheduled for next gen OpenLane
#2158
opened Oct 2, 2024 by
maliberty
Yosys Tool Crashing at "Executing ABC" with no errorcode
question
The user needs help
waiting on op
Information has been requested from the Issue Author
#2152
opened Sep 13, 2024 by
krupatishbi
getting max capacitance and max slew violations at some corners while doing sta
question
The user needs help
waiting on op
Information has been requested from the Issue Author
#2144
opened Aug 2, 2024 by
Sanchit-Gupta10
Error: multi_corner.tcl line 43
waiting on op
Information has been requested from the Issue Author
#2123
opened May 20, 2024 by
fazliemre
Generating the PDN fails at the "Hierarchical chip design (with macros)" tutorial
bug
Something isn't working
documentation
Improvements or additions to documentation
#2121
opened May 7, 2024 by
kietuan
Enable rtl_macro_placer feature
enhancement
New feature or request
OpenLane 2
Scheduled for next gen OpenLane
#2117
opened Apr 12, 2024 by
vijayank88
Unbalanced buffer insertion on high fanout designs
question
The user needs help
#2090
opened Feb 6, 2024 by
Dolu1990
flow succeeds even if clock signal wire is unconnected / doesn't exist
Yosys
This issue is related to yosys
#2083
opened Jan 10, 2024 by
mattvenn
Getting -from and -to are no longer supported
OpenLane 2
Scheduled for next gen OpenLane
#2081
opened Jan 2, 2024 by
ShankarSNP
ERROR]: Synthesis failed. Signal not matching port size. Search for 'Resizing cell port'
waiting on op
Information has been requested from the Issue Author
#2078
opened Dec 28, 2023 by
alishan1213
[ERROR STA-0026] unterminated string constant
blocked
This issue is blocked on a bugfix or enhancement of another repository or tool
bug
Something isn't working
OpenROAD
An issue with an OpenROAD component
#2063
opened Dec 10, 2023 by
thesourcerer8
CURRENT_ODB is unset
when follow Designing a chip with an OpenRAM (sky130)
bug
#2032
opened Oct 30, 2023 by
PeterBorisenko
Using Openlane for symmetric routing
enhancement
New feature or request
#2031
opened Oct 30, 2023 by
jchin2
Downloadable document
documentation
Improvements or additions to documentation
enhancement
New feature or request
#2016
opened Oct 11, 2023 by
alwinshaju08
Move fetch_library_info to OpenLane backbone
enhancement
New feature or request
#2008
opened Oct 1, 2023 by
kareefardi
Routing not respecting PR Boundary
blocked
This issue is blocked on a bugfix or enhancement of another repository or tool
bug
Something isn't working
OpenROAD
An issue with an OpenROAD component
#2006
opened Sep 27, 2023 by
marwaneltoukhy
Placement Resizer optimization error with recently version of OpenLane
bug
Something isn't working
#1982
opened Sep 11, 2023 by
Baungarten-CINVESTAV
Please add hooks for user scripts into openroad tcl files
enhancement
New feature or request
OpenLane 2
Scheduled for next gen OpenLane
#1964
opened Sep 1, 2023 by
chaufe
FP_PDN_CFG Met3 and Met4 not connecting to macro's defined power rails
question
The user needs help
#1947
opened Aug 17, 2023 by
jchin2
Previous Next
ProTip!
Follow long discussions with comments:>50.