Clarify semantics of sfence.vma with rs1 != 0 (riscv#515)

Based on discussion on the mailing list, the instruction fences accesses not just to one leaf PTE but to any leaf PTE that includes the address (subject to address space constraints specified via rs2).

Clarify that various reset events are relative to hart reset

Clarify that mtimecmp comparison is unsigned

Clarify that RV64 accesses to mtime/mtimecmp are atomic

Make misaligned exception text more generic than RV32

Clarify that the EEI defines misaligned FP ld/st behavior

Avoid "should" when describing a mandate

Resolves riscv#510

Non misleading bit width expression in chapter C (riscv#506)

Add note about AUIPC+JALR range in RV64

Clarify that FENCE + remote FENCE.I is insufficient for local hart (r…

…iscv#503)

This sequence only synchronises the remote harts; the local hart still
needs to perform a normal FENCE.I.