Clarify that various reset events are relative to hart reset

src/machine.tex

@@ -1722,7 +1722,7 @@ \subsection{Hardware Performance Monitor}
 retired.  The {\tt mcycle} and {\tt minstret} registers have 64-bit
 precision on all RV32 and RV64 systems.
 
-The counter registers have an arbitrary value after system reset, and
+The counter registers have an arbitrary value after the hart is reset, and
 can be written with a given value. Any CSR write takes effect after
 the writing instruction has otherwise completed.
 The {\tt mcycle} CSR may be shared between harts on the same core, in which
@@ -2997,8 +2997,8 @@ \section{Physical Memory Protection}
 accesses for virtual-address translation, for which the effective
 privilege mode is S.  Optionally, PMP checks may additionally apply
 to M-mode accesses, in which case the PMP registers themselves are
-locked, so that even M-mode software cannot change them without
-a system reset.  In effect, PMP can {\em grant} permissions to S and U
+locked, so that even M-mode software cannot change them until the hart is
+reset.  In effect, PMP can {\em grant} permissions to S and U
 modes, which by default have none, and can {\em revoke} permissions
 from M-mode, which by default has full permissions.
 
@@ -3327,7 +3327,7 @@ \subsubsection*{Locking and Privilege Mode}
 
 The L bit indicates that the PMP entry is locked, i.e., writes to the
 configuration register and associated address registers are ignored.  Locked
-PMP entries may only be unlocked with a system reset.  If PMP entry $i$ is
+PMP entries remain locked until the hart is reset.  If PMP entry $i$ is
 locked, writes to {\tt pmp}$i${\tt cfg} and {\tt pmpaddr}$i$ are ignored.
 Additionally, if {\tt pmp}$i${\tt cfg}.A is set to TOR, writes to {\tt
 pmpaddr}$i$-1 are ignored.