Clarify that the EEI defines misaligned FP ld/st behavior

src/f.tex

@@ -370,6 +370,10 @@ \section{Single-Precision Load and Store Instructions}
 FLW and FSW do not modify the bits being transferred; in particular, the
 payloads of non-canonical NaNs are preserved.
 
+As described in Section~\ref{sec:rv32:ldst}, the EEI defines whether
+misaligned floating-point loads and stores are handled invisibly or raise
+a contained or fatal trap.
+
 \section{Single-Precision Floating-Point Computational Instructions}
 \label{sec:single-float-compute}
 

src/rv32.tex

@@ -994,6 +994,7 @@ \subsubsection*{Conditional Branches}
 \end{commentary}
 
 \section{Load and Store Instructions}
+\label{sec:rv32:ldst}
 
 RV32I is a load-store architecture, where only load and store
 instructions access memory and arithmetic instructions only operate on