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Clarify semantics of sfence.vma with rs1 != 0 (riscv#515)
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Based on discussion on the mailing list, the instruction fences accesses not just to one leaf PTE but to any leaf PTE that includes the address (subject to address space constraints specified via rs2).
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fintelia authored Apr 24, 2020
1 parent a1c7d25 commit 0e6e1d4
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4 changes: 2 additions & 2 deletions src/supervisor.tex
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Expand Up @@ -1041,10 +1041,10 @@ \subsection{Supervisor Memory-Management Fence Instruction}
Accesses to {\em global} mappings (see Section~\ref{sec:translation})
are not ordered.
\item If {\em rs1}$\neq${\tt x0} and {\em rs2}={\tt x0}, the fence orders
only reads and writes made to the leaf page table entry corresponding
only reads and writes made to leaf page table entries corresponding
to the virtual address in {\em rs1}, for all address spaces.
\item If {\em rs1}$\neq${\tt x0} and {\em rs2}$\neq${\tt x0}, the fence
orders only reads and writes made to the leaf page table entry
orders only reads and writes made to leaf page table entries
corresponding to the virtual address in {\em rs1}, for the address
space identified by integer register {\em rs2}.
Accesses to global mappings are not ordered.
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