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Do not generate SystemVerilog parameter syntax when there are 0 parameters #498

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merged 1 commit into from
Jul 30, 2024
Merged

Do not generate SystemVerilog parameter syntax when there are 0 parameters #498

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4 changes: 2 additions & 2 deletions lib/src/synthesizers/systemverilog.dart
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Original file line number Diff line number Diff line change
Expand Up @@ -102,7 +102,7 @@ class SystemVerilogSynthesizer extends Synthesizer {
final connectionsStr = connections.join(',');

var parameterString = '';
if (parameters != null) {
if (parameters != null && parameters.isNotEmpty) {
final parameterContents =
parameters.entries.map((e) => '.${e.key}(${e.value})').join(',');
parameterString = '#($parameterContents)';
Expand Down Expand Up @@ -485,7 +485,7 @@ class _SystemVerilogSynthesisResult extends SynthesisResult {
String? _verilogParameters(Module module) {
if (module is SystemVerilog) {
final defParams = module.definitionParameters;
if (defParams == null) {
if (defParams == null || defParams.isEmpty) {
return null;
}

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37 changes: 37 additions & 0 deletions test/sv_param_passthrough_test.dart
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Expand Up @@ -114,6 +114,35 @@ class LeafNodeExternal extends ModWithParamPassthrough {
String? definitionVerilog(String definitionType) => '';
}

class TopForEmptyParams extends ModWithParamPassthrough {
Logic get b => output('b');
TopForEmptyParams(Logic a,
{super.definitionName = 'top_for_empty',
super.instantiationParameters = const {},
super.name = 'top'})
: super([]) {
a = addInput('a', a, width: 8);
addOutput('b', width: 8);
b <= LeafNodeExternalEmptyParams(a).b;
}
}

class LeafNodeExternalEmptyParams extends ModWithParamPassthrough {
Logic get b => output('b');
LeafNodeExternalEmptyParams(Logic a,
{super.definitionName = 'leaf_node',
super.instantiationParameters = const {},
super.name = 'leaf'})
: super([]) {
a = addInput('a', a, width: 8);
addOutput('b', width: 8);
}

// leaf node should not generate any SV, like external
@override
String? definitionVerilog(String definitionType) => '';
}

void main() {
test('passthrough params custom system verilog', () async {
final mod = Top(Logic(width: 8));
Expand All @@ -128,4 +157,12 @@ void main() {
'test/sv_param_passthrough.sv', // include external SV
]);
});

test('empty params does include param # in generated system verilog',
() async {
final mod = TopForEmptyParams(Logic(width: 8));
await mod.build();
final sv = mod.generateSynth();
expect(sv.contains('#'), isFalse);
});
}
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