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Do not generate SystemVerilog parameter syntax when there are 0 parameters #498

Merged
merged 1 commit into from
Jul 30, 2024
Merged

Do not generate SystemVerilog parameter syntax when there are 0 parameters #498

merged 1 commit into from
Jul 30, 2024

Commits on Jul 29, 2024

  1. Do not gen empty param sv

    @mkorbel1
    mkorbel1 committed Jul 29, 2024
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