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98 Open 149 Closed
98 Open 149 Closed
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Issues list

Async reset can cause signals to show up late in generated waveforms in some cases bug Something isn't working
#528 opened Oct 29, 2024 by mkorbel1
Consts that inferWidth to 0-width generate SystemVerilog with 0-width bug Something isn't working
#527 opened Oct 14, 2024 by mkorbel1
Add documentation on Interfaces driving/receiving each other documentation Improvements or additions to documentation enhancement New feature or request
#524 opened Oct 4, 2024 by mkorbel1
Allow swizzling on Iterable instead of just List enhancement New feature or request good first issue Good for newcomers
#523 opened Oct 4, 2024 by mkorbel1
When replicating by 1, just return the 1 signal enhancement New feature or request good first issue Good for newcomers
#522 opened Oct 4, 2024 by mkorbel1
Add documentation for selectIndex and selectFrom in the user guide documentation Improvements or additions to documentation enhancement New feature or request
#520 opened Oct 4, 2024 by mkorbel1
PairInterface cloning should include subInterfaces as well enhancement New feature or request
#519 opened Oct 4, 2024 by mkorbel1
Swizzle/Subset for LogicNet's enhancement New feature or request
#518 opened Oct 4, 2024 by mkorbel1
@mkorbel1
Expose & infer name on automations like flop, cases, mux, etc. enhancement New feature or request good first issue Good for newcomers
#517 opened Oct 3, 2024 by mkorbel1
A way to dispose of unnecessary Simulator subscriptions enhancement New feature or request
#516 opened Oct 2, 2024 by mkorbel1
1
Interface._setPort assertion should be an exception bug Something isn't working
#514 opened Sep 26, 2024 by mkorbel1
Add SystemVerilog generation control for top of module definition enhancement New feature or request
#513 opened Sep 26, 2024 by mkorbel1
Add automation to help with Lists of signals as ports of a module enhancement New feature or request
#512 opened Sep 18, 2024 by mkorbel1
Dart Static Metaprogramming (macros) for common automation enhancement New feature or request
#511 opened Sep 18, 2024 by mkorbel1
Partial assignment of Logic indices enhancement New feature or request
#510 opened Sep 17, 2024 by mkorbel1
"Default" values for FiniteStateMachines enhancement New feature or request
#509 opened Sep 17, 2024 by mkorbel1
Consistency for math helpers (isPow2, log2Ceil, etc.) enhancement New feature or request
#508 opened Sep 17, 2024 by mkorbel1
Best practices documentation for constructing reusable hardware documentation Improvements or additions to documentation enhancement New feature or request
#507 opened Sep 16, 2024 by mkorbel1
1
Deprecate Port, move to Logic.port for API consistency enhancement New feature or request
#506 opened Sep 11, 2024 by mkorbel1
Support VHDL enhancement New feature or request
#493 opened Jun 13, 2024 by mkorbel1
Buggy Assertion that tends to check for submodule contained in a module bug Something isn't working
#488 opened Jun 6, 2024 by sshankar4
@mkorbel1
Protect Const from having its value modified enhancement New feature or request
#486 opened May 30, 2024 by mkorbel1
Add selectIndex directly to LogicArray (and Logic?) to enable one-liner accesses in generated SV. enhancement New feature or request
#484 opened Apr 29, 2024 by mkorbel1
Add better tests for simulator phasing enhancement New feature or request
#479 opened Apr 2, 2024 by mkorbel1
Fixed point support enhancement New feature or request
#470 opened Feb 29, 2024 by samimia-swks
3
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