v0.6.11

• New features:
  • Add support for HDL synthesis tool specific HDL generation:
    • New -clash-hdlsyn Vivado flag to generate HDL tweaked for Xilinx Vivado
  • Preserve more Haskell names in generated HDL #128
• Fixes bugs:
  • VHDL: Vivado fails to infer block ram #127
    • Users must use the -clash-hdlsyn Vivado flag in order to generate Xilinx Vivado specific HDL for which Vivado can infer block RAM.

v0.6.10

• New features:
  • hdl files can be written to a directory (set by the -clash-hdldir flag) other than the current working directory #125.
    Also respects the -outputdir directory, unless:
    • -clash-hdldir is set to a different directory.
    • -hidir, -stubdir, and -dumbdir are not the same directory as -odir
• Fixes bugs:
  • caseCon transformation does not work on non-exhaustive case-expressions #123
  • VHDL: insufficient type-qualifiers for concatenation operator #121
  • Primitive reductions don't look through Signal #126

v0.6.9

• New features:
  • Support for Debug.Trace.trace, thanks to @ggreif
• Fixes bugs:
  • case undefined of ... should reduce to undefined #116
  • VHDL/SystemVerilog: BlockRAM elements must be bit vectors #113
  • Type families obscure eligibility for synthesis #114

v0.6.8

• New features:
  • Support for Haskell's: Char, Int8, Int16, Int32, Int64, Word, Word8, Word16, Word32, Word64.
  • Int/Word/Integer bitwidth for generated HDL is configurable using the -clash-intwidth=N flag, where N can be either 32 or 64.
• Fixes bugs:
  • Cannot reduce case error ... of ... to error ... #109

v0.6.7

• Support for unbound-generics-0.3
• New features:
  • Only look for 'topEntity' in the root module. #22
• Fixes bugs:
  • Unhelpful error message when GHC is not in PATH #104

v0.6.6

• New features:
  • Remove all existing HDL files before generating new ones. This can be disabled by the -clash-noclean flag. #96
  • Support for clash-prelude 0.10.4

v0.6.5

• Fixes bugs:
  • Integer literals used as arguments not always properly annotated with their type.
  • Verilog: Name collision in verilog code #93
  • (System)Verilog: Integer literals missing "32'sd" prefix when used in assignments.
  • VHDL: Integer literals should only be capped to 32-bit when used in assignments.
  • Verilog: HO-primitives incorrect for nested vectors.

v0.6.4

• Fixes bugs:
  • Reversing alternatives is not meaning preserving for literal patterns #91
  • DEC: root of the case-tree must contain at least 2 alternatives #92
  • Do not generate overlapping literal patterns in VHDL #91

v0.6.3

• New features:
  • Improve DEC transformation: consider alternatives before the subject when checking for disjoint expressions.
• Fixes bugs:
  • DEC: don't generate single-branch case-expressions #90

v0.6.2

• New features:
  • Support clash-prelude 0.10.2
• Fixes bugs:
  • CLaSH interpreter was reading '.ghci' file instead of '.clashi' file #87
  • DEC: Subject and alternatives are not disjoint #88