v0.6.5

• Fixes bugs:
  • Integer literals used as arguments not always properly annotated with their type.
  • Verilog: Name collision in verilog code #93
  • (System)Verilog: Integer literals missing "32'sd" prefix when used in assignments.
  • VHDL: Integer literals should only be capped to 32-bit when used in assignments.
  • Verilog: HO-primitives incorrect for nested vectors.