v0.6.9

christiaanb released this 29 Jan 10:54

· 4720 commits to master since this release

7427102

New features:
- Support for Debug.Trace.trace, thanks to @ggreif
Fixes bugs:
- case undefined of ... should reduce to undefined #116
- VHDL/SystemVerilog: BlockRAM elements must be bit vectors #113
- Type families obscure eligibility for synthesis #114

Assets 2