Releases: chipsalliance/caliptra-sw
Releases · chipsalliance/caliptra-sw
release_v20231027_1
CI: Update Caliptra RTL (#1001)
release_v20231027_0
Run all driver tests in the FPGA CI workflow.
release_v20231026_0
Create FMC test cases document and update FMC test harness. (#985)
release_v20231025_0
Sign response struct field change Fix signature_s field in libcaliptra DPE sign response
release_v20231024_0
Extract API logic from caliptra_common into new caliptra-api crate. (…
release_v20231021_0
fpga_realtime: Service etrng requests from separate thread. (#983) We are seeing intermittent failures from tests that let the hardware model run in the background while they do something else. When the test takes longer than 25ms to respond to etrng requests, the firmware times out. Servicing these requests from a separate thread should make things more reliable.
release_v20231020_0
Adds caliptra_set_wdt_timeout to C API (#977)
release_v20231019_0
Output warning message in libcaliptra build if RTL repo isn't specified When libcaliptra is built from inside caliptra-sw, it can default to use the hw-latest submodule. Output a warning that the default behavior is happening. This will help in troubleshooting if the submodule isn't present or is at an unexpected location.
release_v20231018_0
FPGA CI: Always use latest GHA runner version. (#973) And rebuild the FPGA image twice a week.
release_v20231017_0
FMC : Dump RISCV trap record information to the SoC interface.