Skip to content

Releases: chipsalliance/caliptra-sw

release_v20231027_1

27 Oct 19:31
bccb2ad
Compare
Choose a tag to compare
CI: Update Caliptra RTL (#1001)

release_v20231027_0

27 Oct 10:34
Compare
Choose a tag to compare
Run all driver tests in the FPGA CI workflow.

release_v20231026_0

26 Oct 10:33
6d6e908
Compare
Choose a tag to compare
Create FMC test cases document and update FMC test harness. (#985)

release_v20231025_0

25 Oct 10:35
0a409b7
Compare
Choose a tag to compare
Sign response struct field change

Fix signature_s field in libcaliptra DPE sign response

release_v20231024_0

24 Oct 10:32
2b83838
Compare
Choose a tag to compare
Extract API logic from caliptra_common into new caliptra-api crate. (…

release_v20231021_0

21 Oct 10:32
f23b034
Compare
Choose a tag to compare
fpga_realtime: Service etrng requests from separate thread. (#983)

We are seeing intermittent failures from tests that let the hardware
model run in the background while they do something else. When the test
takes longer than 25ms to respond to etrng requests, the firmware times
out. Servicing these requests from a separate thread should make things
more reliable.

release_v20231020_0

20 Oct 10:33
80584f4
Compare
Choose a tag to compare
Adds caliptra_set_wdt_timeout to C API (#977)

release_v20231019_0

19 Oct 10:33
Compare
Choose a tag to compare
Output warning message in libcaliptra build if RTL repo isn't specified

When libcaliptra is built from inside caliptra-sw, it can default to use
the hw-latest submodule. Output a warning that the default behavior is
happening. This will help in troubleshooting if the submodule isn't
present or is at an unexpected location.

release_v20231018_0

18 Oct 10:32
9e5e655
Compare
Choose a tag to compare
FPGA CI: Always use latest GHA runner version. (#973)

And rebuild the FPGA image twice a week.

release_v20231017_0

17 Oct 10:34
Compare
Choose a tag to compare
FMC : Dump RISCV trap record information to the SoC interface.