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CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems
README.md

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🔗 chipsalliance.org | 📫 [email protected]

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.

The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

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  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

    Scala 3.9k 589

  2. rocket-chip rocket-chip Public

    Rocket Chip Generator

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  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    C++ 1.3k 200

  4. riscv-dv riscv-dv Public

    Random instruction generator for RISC-V processor verification

    Python 1k 322

  5. Cores-VeeR-EH1 Cores-VeeR-EH1 Public

    VeeR EH1 core

    SystemVerilog 810 219

  6. firrtl firrtl Public archive

    Flexible Intermediate Representation for RTL

    Scala 720 175

Repositories

Showing 10 of 107 repositories
  • chisel Public

    Chisel: A Modern Hardware Design Language

    chipsalliance/chisel’s past year of commit activity
    Scala 3,921 Apache-2.0 589 306 (1 issue needs help) 155 Updated Sep 20, 2024
  • chisel-nix Public

    Nix scripts used to manage the chisel projects.

    chipsalliance/chisel-nix’s past year of commit activity
    Nix 20 1 0 1 Updated Sep 20, 2024
  • t1 Public
    chipsalliance/t1’s past year of commit activity
    Scala 112 Apache-2.0 21 17 21 Updated Sep 20, 2024
  • synlig-logs Public
    chipsalliance/synlig-logs’s past year of commit activity
    0 0 0 0 Updated Sep 20, 2024
  • synlig Public

    SystemVerilog support for Yosys

    chipsalliance/synlig’s past year of commit activity
    Verilog 157 Apache-2.0 21 65 7 Updated Sep 20, 2024
  • sv-tests-results Public

    Output of the sv-tests runs.

    chipsalliance/sv-tests-results’s past year of commit activity
    HTML 5 1 0 0 Updated Sep 20, 2024
  • verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    chipsalliance/verible’s past year of commit activity
    C++ 1,326 200 466 (15 issues need help) 22 Updated Sep 20, 2024
  • sv-tests Public

    Test suite designed to check compliance with the SystemVerilog standard.

    chipsalliance/sv-tests’s past year of commit activity
    SystemVerilog 285 ISC 75 45 (5 issues need help) 22 Updated Sep 20, 2024
  • aib-phy-hardware Public

    Advanced Interface Bus (AIB) die-to-die hardware open source

    chipsalliance/aib-phy-hardware’s past year of commit activity
    Verilog 118 Apache-2.0 29 0 1 Updated Sep 20, 2024
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    chipsalliance/caliptra-sw’s past year of commit activity
    Rust 52 Apache-2.0 39 84 54 Updated Sep 19, 2024
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