release_v20231123_0

release: Run tests under sw-emulator before releasing.

This will run all combinations of itrng/etrng and logging/no-logging.

release_v20231122_1

[test] Add warm reset tests to ROM integration test suite (#1086)

release_v20231122_0

[test] Add warm reset tests to ROM integration test suite (#1086)

release_v20231121_0

Add test triggering cpu fault and check extended error info

To do this, we write an illegal instruction at the rom_entry
symbol in the rom binary.

release_v20231118_0

Extend the measurement into PCR31 in RT stash_measurement

release_v20231117_0

[fix] CFI improvement (#1087)

Co-authored-by: Kor Nielsen <[email protected]>

release_v20231116_0

Add DPE verification tests and test gaps to RT test coverage doc

release_v20231115_0

caliptra-api: Use wrapping arithmetic for checksum calculation. (#1072)

This is necessary because it is possible to make verify_checksum() panic
when compiled for debug:

release_v20231114_0

Emulation code coverage :  persist and merge coverage bitmaps (#992)

* This commit extends sw-emulator coverage functionality so the coverage bitmap of indiividual test runs can be
dumped to the file system and subsequently merged so the coverage can be calculated.

* misc fixes

* Remove expensive .clone() call.

---------

Co-authored-by: Kor Nielsen <[email protected]>

release_v20231111_0

Work-around timing-out verilator-nightly tests (#1058)

* driver tests: Reduce number of iterations of test_sha1.

This test times out under verilator. By reducing the number of
iterations it can pass.

* Don't run ecdsa_cmd_run_wycheproof() test in verilator nightly.

This test is too slow to run without timing out. It will still run on
the FPGA and sw-emulator.

* Don't run slow ROM validation tests in verilator nightly.

These tests are too slow to run without timing out. They will still run
on the FPGA and sw-emulator.