Work-around timing-out verilator-nightly tests (#1058)

* driver tests: Reduce number of iterations of test_sha1.

This test times out under verilator. By reducing the number of
iterations it can pass.

* Don't run ecdsa_cmd_run_wycheproof() test in verilator nightly.

This test is too slow to run without timing out. It will still run on
the FPGA and sw-emulator.

* Don't run slow ROM validation tests in verilator nightly.

These tests are too slow to run without timing out. They will still run
on the FPGA and sw-emulator.

drivers/test-fw/src/bin/sha1_tests.rs

@@ -51,12 +51,12 @@ fn test_digest3() {
 }
 
 fn test_op1() {
-    let expected = Array4xN([0x34aa973c, 0xd4c4daa4, 0xf61eeb2b, 0xdbad2731, 0x6534016f]);
+    let expected = Array4xN([0x521d84ef, 0xcae113d0, 0x00a14796, 0x8b508e06, 0x7cb60184]);
     const DATA: [u8; 1000] = [0x61; 1000];
     let mut digest = Array4x5::default();
     let mut sha = Sha1::default();
     let mut digest_op = sha.digest_init().unwrap();
-    for _ in 0..1_000 {
+    for _ in 0..300 {
         assert!(digest_op.update(&DATA).is_ok());
     }
     let actual = digest_op.finalize(&mut digest);

rom/dev/tests/rom_integration_tests/test_image_validation.rs

@@ -234,6 +234,9 @@ fn test_preamble_vendor_ecc_pubkey_revocation() {
 
 #[test]
 fn test_preamble_vendor_lms_pubkey_revocation() {
+    // this test is too slow to run in the verilator nightly
+    #![cfg_attr(all(not(feature = "slow_tests"), feature = "verilator"), ignore)]
+
     let rom = caliptra_builder::build_firmware_rom(&ROM_WITH_UART).unwrap();
     const LAST_KEY_IDX: u32 = VENDOR_LMS_KEY_COUNT - 1;
 
@@ -287,6 +290,9 @@ fn test_preamble_vendor_lms_pubkey_revocation() {
 
 #[test]
 fn test_preamble_vendor_lms_optional_no_pubkey_revocation_check() {
+    // this test is too slow to run in the verilator nightly
+    #![cfg_attr(all(not(feature = "slow_tests"), feature = "verilator"), ignore)]
+
     let rom = caliptra_builder::build_firmware_rom(&ROM_WITH_UART).unwrap();
 
     for idx in 0..VENDOR_LMS_KEY_COUNT {

runtime/Cargo.toml

@@ -47,6 +47,7 @@ itrng = ["caliptra-hw-model/itrng"]
 riscv = ["caliptra-cpu/riscv"]
 std = ["ufmt/std", "caliptra_common/std"]
 test_only_commands = []
+slow_tests = []
 verilator = ["caliptra-hw-model/verilator"]
 fips_self_test=[]
 fpga_realtime = ["caliptra-drivers/fpga_realtime"]

runtime/tests/runtime_integration_tests/ecdsa.rs

@@ -15,6 +15,9 @@ use zerocopy::{AsBytes, FromBytes};
 
 #[test]
 fn ecdsa_cmd_run_wycheproof() {
+    // This test is too slow to run as part of the verilator nightly.
+    #![cfg_attr(all(not(feature = "slow_tests"), feature = "verilator"), ignore)]
+
     let mut model = run_rt_test(None, None, None);
 
     model.step_until(|m| {