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alexforencich

Drop entire write operation on address decode fail in axi_interconnect

Oct 19, 2020

cd06f0b · Oct 19, 2020

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This branch is 67 commits behind alexforencich/verilog-axi:master.

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Name		Name	Last commit message	Last commit date
parent directory ..
arbiter.v		arbiter.v	Add arbiter and priority encoder modules	Aug 23, 2018
axi_adapter.v		axi_adapter.v	Add parameter documentation	Jul 25, 2019
axi_adapter_rd.v		axi_adapter_rd.v	Include instance names in error messages	Jul 25, 2019
axi_adapter_wr.v		axi_adapter_wr.v	Include instance names in error messages	Jul 25, 2019
axi_axil_adapter.v		axi_axil_adapter.v	Add parameter documentation	Jul 25, 2019
axi_axil_adapter_rd.v		axi_axil_adapter_rd.v	Include instance names in error messages	Jul 25, 2019
axi_axil_adapter_wr.v		axi_axil_adapter_wr.v	Include instance names in error messages	Jul 25, 2019
axi_cdma.v		axi_cdma.v	Include instance names in error messages	Jul 25, 2019
axi_cdma_desc_mux.v		axi_cdma_desc_mux.v	Include instance names in error messages	Jul 25, 2019
axi_crossbar.v		axi_crossbar.v	Add default addressing capability to interconnect modules	Oct 31, 2019
axi_crossbar_addr.v		axi_crossbar_addr.v	Add default addressing capability to interconnect modules	Oct 31, 2019
axi_crossbar_rd.v		axi_crossbar_rd.v	Add default addressing capability to interconnect modules	Oct 31, 2019
axi_crossbar_wr.v		axi_crossbar_wr.v	Add default addressing capability to interconnect modules	Oct 31, 2019
axi_dma.v		axi_dma.v	Add parameter documentation	Jul 25, 2019
axi_dma_desc_mux.v		axi_dma_desc_mux.v	Include instance names in error messages	Jul 25, 2019
axi_dma_rd.v		axi_dma_rd.v	Bypass check when unneeded	Oct 31, 2019
axi_dma_wr.v		axi_dma_wr.v	Bypass check when unneeded	Oct 31, 2019
axi_dp_ram.v		axi_dp_ram.v	Fix backpressure bug	Apr 13, 2020
axi_fifo.v		axi_fifo.v	Add parameter documentation	Jul 25, 2019
axi_fifo_rd.v		axi_fifo_rd.v	Rewrite resets	Aug 27, 2020
axi_fifo_wr.v		axi_fifo_wr.v	Rewrite resets	Aug 27, 2020
axi_interconnect.v		axi_interconnect.v	Drop entire write operation on address decode fail in axi_interconnect	Oct 19, 2020
axi_ram.v		axi_ram.v	Use correct RAM size for initialization	Nov 24, 2019
axi_ram_rd_if.v		axi_ram_rd_if.v	Include instance names in error messages	Jul 25, 2019
axi_ram_wr_if.v		axi_ram_wr_if.v	Include instance names in error messages	Jul 25, 2019
axi_ram_wr_rd_if.v		axi_ram_wr_rd_if.v	Add parameter documentation	Jul 25, 2019
axi_register.v		axi_register.v	Add parameter documentation	Jul 25, 2019
axi_register_rd.v		axi_register_rd.v	Add parameter documentation	Jul 25, 2019
axi_register_wr.v		axi_register_wr.v	Add parameter documentation	Jul 25, 2019
axil_adapter.v		axil_adapter.v	Add parameter documentation	Jul 25, 2019
axil_adapter_rd.v		axil_adapter_rd.v	Include instance names in error messages	Jul 25, 2019
axil_adapter_wr.v		axil_adapter_wr.v	Include instance names in error messages	Jul 25, 2019
axil_cdc.v		axil_cdc.v	Add parameter documentation	Jul 25, 2019
axil_cdc_rd.v		axil_cdc_rd.v	Add parameter documentation	Jul 25, 2019
axil_cdc_wr.v		axil_cdc_wr.v	Add parameter documentation	Jul 25, 2019
axil_dp_ram.v		axil_dp_ram.v	Use correct RAM size for initialization	Nov 24, 2019
axil_interconnect.v		axil_interconnect.v	Add default addressing capability to interconnect modules	Oct 31, 2019
axil_ram.v		axil_ram.v	Use correct RAM size for initialization	Nov 24, 2019
axil_register.v		axil_register.v	Add parameter documentation	Jul 25, 2019
axil_register_rd.v		axil_register_rd.v	Add parameter documentation	Jul 25, 2019
axil_register_wr.v		axil_register_wr.v	Add parameter documentation	Jul 25, 2019
priority_encoder.v		priority_encoder.v	Rewrite priority encoder to remove recusive construction	Aug 18, 2020
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