Rewrite resets

bmindur · Aug 27, 2020 · 2c6185c · 2c6185c
1 parent 00e2756
commit 2c6185c
Show file tree

Hide file tree

Showing 2 changed files with 58 additions and 60 deletions.
diff --git a/rtl/axi_fifo_rd.v b/rtl/axi_fifo_rd.v
@@ -263,17 +263,8 @@ if (FIFO_DELAY) begin
     end
 
     always @(posedge clk) begin
-        if (rst) begin
-            state_reg <= STATE_IDLE;
-            count_reg <= count_next;
-            m_axi_arvalid_reg <= 1'b0;
-            s_axi_arready_reg <= 1'b0;
-        end else begin
-            state_reg <= state_next;
-            count_reg <= {COUNT_WIDTH{1'b0}};
-            m_axi_arvalid_reg <= m_axi_arvalid_next;
-            s_axi_arready_reg <= s_axi_arready_next;
-        end
+        state_reg <= state_next;
+        count_reg <= count_next;
 
         m_axi_arid_reg <= m_axi_arid_next;
         m_axi_araddr_reg <= m_axi_araddr_next;
@@ -286,6 +277,15 @@ if (FIFO_DELAY) begin
         m_axi_arqos_reg <= m_axi_arqos_next;
         m_axi_arregion_reg <= m_axi_arregion_next;
         m_axi_aruser_reg <= m_axi_aruser_next;
+        m_axi_arvalid_reg <= m_axi_arvalid_next;
+        s_axi_arready_reg <= s_axi_arready_next;
+
+        if (rst) begin
+            state_reg <= STATE_IDLE;
+            count_reg <= {COUNT_WIDTH{1'b0}};
+            m_axi_arvalid_reg <= 1'b0;
+            s_axi_arready_reg <= 1'b0;
+        end
     end
 end else begin
     // bypass AR channel
@@ -331,17 +331,16 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        wr_ptr_reg <= {FIFO_ADDR_WIDTH+1{1'b0}};
-    end else begin
-        wr_ptr_reg <= wr_ptr_next;
-    end
-
+    wr_ptr_reg <= wr_ptr_next;
     wr_addr_reg <= wr_ptr_next;
 
     if (write) begin
         mem[wr_addr_reg[FIFO_ADDR_WIDTH-1:0]] <= m_axi_r;
     end
+
+    if (rst) begin
+        wr_ptr_reg <= {FIFO_ADDR_WIDTH+1{1'b0}};
+    end
 end
 
 // Read logic
@@ -367,19 +366,19 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        rd_ptr_reg <= {FIFO_ADDR_WIDTH+1{1'b0}};
-        mem_read_data_valid_reg <= 1'b0;
-    end else begin
-        rd_ptr_reg <= rd_ptr_next;
-        mem_read_data_valid_reg <= mem_read_data_valid_next;
-    end
-
+    rd_ptr_reg <= rd_ptr_next;
     rd_addr_reg <= rd_ptr_next;
 
+    mem_read_data_valid_reg <= mem_read_data_valid_next;
+
     if (read) begin
         mem_read_data_reg <= mem[rd_addr_reg[FIFO_ADDR_WIDTH-1:0]];
     end
+
+    if (rst) begin
+        rd_ptr_reg <= {FIFO_ADDR_WIDTH+1{1'b0}};
+        mem_read_data_valid_reg <= 1'b0;
+    end
 end
 
 // Output register
@@ -395,15 +394,15 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        s_axi_rvalid_reg <= 1'b0;
-    end else begin
-        s_axi_rvalid_reg <= s_axi_rvalid_next;
-    end
+    s_axi_rvalid_reg <= s_axi_rvalid_next;
 
     if (store_output) begin
         s_axi_r_reg <= mem_read_data_reg;
     end
+
+    if (rst) begin
+        s_axi_rvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/rtl/axi_fifo_wr.v b/rtl/axi_fifo_wr.v
@@ -294,18 +294,9 @@ if (FIFO_DELAY) begin
     end
 
     always @(posedge clk) begin
-        if (rst) begin
-            state_reg <= STATE_IDLE;
-            hold_reg <= 1'b1;
-            m_axi_awvalid_reg <= 1'b0;
-            s_axi_awready_reg <= 1'b0;
-        end else begin
-            state_reg <= state_next;
-            hold_reg <= hold_next;
-            m_axi_awvalid_reg <= m_axi_awvalid_next;
-            s_axi_awready_reg <= s_axi_awready_next;
-        end
+        state_reg <= state_next;
 
+        hold_reg <= hold_next;
         count_reg <= count_next;
 
         m_axi_awid_reg <= m_axi_awid_next;
@@ -319,6 +310,15 @@ if (FIFO_DELAY) begin
         m_axi_awqos_reg <= m_axi_awqos_next;
         m_axi_awregion_reg <= m_axi_awregion_next;
         m_axi_awuser_reg <= m_axi_awuser_next;
+        m_axi_awvalid_reg <= m_axi_awvalid_next;
+        s_axi_awready_reg <= s_axi_awready_next;
+
+        if (rst) begin
+            state_reg <= STATE_IDLE;
+            hold_reg <= 1'b1;
+            m_axi_awvalid_reg <= 1'b0;
+            s_axi_awready_reg <= 1'b0;
+        end
     end
 end else begin
     // bypass AW channel
@@ -372,17 +372,16 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        wr_ptr_reg <= {FIFO_ADDR_WIDTH+1{1'b0}};
-    end else begin
-        wr_ptr_reg <= wr_ptr_next;
-    end
-
+    wr_ptr_reg <= wr_ptr_next;
     wr_addr_reg <= wr_ptr_next;
 
     if (write) begin
         mem[wr_addr_reg[FIFO_ADDR_WIDTH-1:0]] <= s_axi_w;
     end
+
+    if (rst) begin
+        wr_ptr_reg <= {FIFO_ADDR_WIDTH+1{1'b0}};
+    end
 end
 
 // Read logic
@@ -408,19 +407,19 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        rd_ptr_reg <= {FIFO_ADDR_WIDTH+1{1'b0}};
-        mem_read_data_valid_reg <= 1'b0;
-    end else begin
-        rd_ptr_reg <= rd_ptr_next;
-        mem_read_data_valid_reg <= mem_read_data_valid_next;
-    end
-
+    rd_ptr_reg <= rd_ptr_next;
     rd_addr_reg <= rd_ptr_next;
 
+    mem_read_data_valid_reg <= mem_read_data_valid_next;
+
     if (read) begin
         mem_read_data_reg <= mem[rd_addr_reg[FIFO_ADDR_WIDTH-1:0]];
     end
+
+    if (rst) begin
+        rd_ptr_reg <= {FIFO_ADDR_WIDTH+1{1'b0}};
+        mem_read_data_valid_reg <= 1'b0;
+    end
 end
 
 // Output register
@@ -436,15 +435,15 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_axi_wvalid_reg <= 1'b0;
-    end else begin
-        m_axi_wvalid_reg <= m_axi_wvalid_next;
-    end
+    m_axi_wvalid_reg <= m_axi_wvalid_next;
 
     if (store_output) begin
         m_axi_w_reg <= mem_read_data_reg;
     end
+
+    if (rst) begin
+        m_axi_wvalid_reg <= 1'b0;
+    end
 end
 
 endmodule