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cyrozap edited this page Apr 8, 2016
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Welcome to the open FPGA tools wiki!
Note: This project is NOT affiliated with OpenFPGA INC.
| Device/Vendor | Status | Note |
|---|---|---|
| Xilinx CoolRunner-II | Most of bitstream mapping done, partial place-and-route, no HDL integration | TODO: merge code from azonenberg's internal SVN |
| Silego Greenpak4 | Can go from HDL to bitstream for most digital functions, no mixed signal yet | Bitstream is publicly documented |
| Cypress PSoC 5(LP)/PSoC 4/PSoC 3 | Not yet started | All UDB (2x PLD + ALU + FIFO) register locations are documented publicly, but the specifics of what each bit in those registers does is not, except for some of the ALU status and control registers. |
TODO: List other projects here to avoid duplicating work
| Project | Description |
|---|---|
| Yosys | Open Verilog synthesis for a number of FPGAs |
| arachne-pnr | Place-and-route for iCE40 FPGAs |
| IceStorm | Bitstream manipulation tools for iCE40 FPGAs |