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Welcome to the open FPGA tools wiki!

Note: This project is NOT affiliated with OpenFPGA INC.

List of sub-projects and status

Device/Vendor	Status	Note
Xilinx CoolRunner-II	Most of bitstream mapping done, partial place-and-route, no HDL integration	TODO: merge code from azonenberg's internal SVN
Silego Greenpak4	Initial progress on C++ object model	Bitstream is publicly doc'd
Cypress PSoC 5(LP)	Not yet started

Other open FPGA toolchain projects

TODO: List other projects here to avoid duplicating work

• Yosys - Open Verilog synthesis for a number of FPGAs
• arachne-pnr - Place-and-route for iCE40 FPGAs
• IceStorm - Bitstream manipulation tools for iCE40 FPGAs