v0.23

Summary

• Fix triggering jitter effect
• Fix DAC buffer enable glitches
• Update libiio v0.18

Changelog

c7ca535 M2k: prepare for v0.23
b75d424 Makefile: Update to Vivado 2018.2 and add workaround for write_sysdev

Changelog Linux:

analogdevicesinc/linux@ba420ca input: adp5589: Add gpio_set_multiple interface
analogdevicesinc/linux@f1ee68e iio: logic: m2k-fabric: Fix EN_AWG1/2 glitches

Changelog buildroot:

analogdevicesinc/buildroot@529a433 Merge pull request #18 from analogdevicesinc/update-libiio-v018-v2
analogdevicesinc/buildroot@161422c package/libiio/libiio.hash: Update Version 0.18 hash after tag move
analogdevicesinc/buildroot@a2a0936 package/libiio/libiio.mk: Update to Version 0.18
analogdevicesinc/buildroot@3599022 linux: strip white-spaces from KERNEL_DTS_NAME
analogdevicesinc/buildroot@c086a0d adi_mb_defconfig: allow buildroot to override the system rootfs
analogdevicesinc/buildroot@43d5c03 microblaze_adi_defconfig: include ADI kernel, ethtool, phy-tool & mii-diag
analogdevicesinc/buildroot@5bd3ee8 microblaze_adi_rootfs_defconfig: split rootfs-only build
analogdevicesinc/buildroot@06d6112 board: adi: microblaze: Include SSH keys
analogdevicesinc/buildroot@9fe51b8 dropbear: add host dropbearkey
analogdevicesinc/buildroot@2f4ea00 Add MicroBlaze support for ADI's platforms
analogdevicesinc/buildroot@2fc84c2 package: libaio: Add MicroBlaze support
analogdevicesinc/buildroot@b995bc4 Merge pull request #15 from analogdevicesinc/rgetz-m2k-html-updates
analogdevicesinc/buildroot@d5b4abb m2k/msd: Update html page, mostly to sync with the pluto page.
analogdevicesinc/buildroot@5747df7 configs/zynq_m2k_defconfig: Update gcc version for 2018.2 toolchain
analogdevicesinc/buildroot@325c7b2 Merge pull request #14 from epiq-alex/pluto
analogdevicesinc/buildroot@886b9ed Modified zynq_sidekiqz2_defconfig with hardfp changes from zynq_pluto_defconfig
analogdevicesinc/buildroot@2e4817b package: libad9361-iio: Bump to Version 0.2 - switch to release mechanism
analogdevicesinc/buildroot@d4c1784 S23udc, S45msd : Tell users if it is a AD9364, or a AD9363
analogdevicesinc/buildroot@b1516ec package/libiio/libiio.mk: Bump to Version 0.17
analogdevicesinc/buildroot@fabd296 Merge pull request #12 from analogdevicesinc/rgetz-html-updates
analogdevicesinc/buildroot@e1476e4 pluto html: Update pluto mass storage page, based on user feedback
analogdevicesinc/buildroot@42b3354 S40network: Be a little more pedantic
analogdevicesinc/buildroot@11e0544 S45msd : indicate if one or two cores are enabled.
analogdevicesinc/buildroot@fea212a configs/zynq_pluto_defconfig: Switch to HF toolchain found in Vivado 2018.2
analogdevicesinc/buildroot@44754e3 package/libiio/libiio.mk: Bump to Version 0.16

Changelog u-boot:

analogdevicesinc/u-boot-xlnx@a2f86f3 Fixed variable definition separators for sidekiqz2

Changelog HDL: (only related commits)

analogdevicesinc/hdl@a3ce8c5 axi_rd_wr_combiner: Add rlast to the AXI MM interface
analogdevicesinc/hdl@1c8172d axi_adc_trigger: Cosmetic update
analogdevicesinc/hdl@44e20d0 axi_adc_trigger: Fix triggering jitter effect
analogdevicesinc/hdl@fc74201 axi_dmac: patch version checking
analogdevicesinc/hdl@804c57a axi_dmac: Remove length alignment requirement for MM interfaces
analogdevicesinc/hdl@7986310 axi_dmac: burst_memory: Add support for using asymmetric memory
analogdevicesinc/hdl@c8900eb axi_dmac: burst_memory: Move src valid bytes resizing to resize_src module
analogdevicesinc/hdl@00090b1 axi_dmac: burst_memory: Consider DMA_LENGTH_ALIGN
analogdevicesinc/hdl@34e89b9 axi_dmac: burst_memory: Reset beat counter at the end of each burst
analogdevicesinc/hdl@764f314 axi_dmac: tb: Allow testing asymmetric interface widths
analogdevicesinc/hdl@46f16f0 axi_dmac/tb: Add support for xsim
analogdevicesinc/hdl@db25ee1 axi_dmac: fix transfer start synchronization
analogdevicesinc/hdl@9d6f3de axi_dmac: assert xfer_request only when ready
analogdevicesinc/hdl@20ac7dc axi_dmac: component level testbench updates
analogdevicesinc/hdl@a4c4e38 axi_dmac: early abort 2d support
analogdevicesinc/hdl@a1cc20e axi_dmac: early abort support
analogdevicesinc/hdl@2f3a959 axi_dmac: request generator reworked to use FSM
analogdevicesinc/hdl@eb40b42 axi_dmac: preparation work for reporting length of partial transfers
analogdevicesinc/hdl@0203cd6 axi_dmac: drive destination eot from source side
analogdevicesinc/hdl@681b619 axi_dmac: wire destination descriptor through source
analogdevicesinc/hdl@8674882 m2k: Downgrade SPI related critical warning, as we use lower clock speed for power reasons
analogdevicesinc/hdl@ef4ceac axi_dmac: Reduce the width of ID signals to minimum
analogdevicesinc/hdl@cff06bd axi_dmac: Use AXI3 for DMAC in Intel projects
analogdevicesinc/hdl@4d8008e axi_dmac: fix address width detection
analogdevicesinc/hdl@5284603 axi_ad9963: Updates for ad_dds phase acc wrapper
analogdevicesinc/hdl@3b319fa axi_ad9963:: Update for CORDIC algorithm
analogdevicesinc/hdl@e79992f axi_dmac: TLAST support for 2d transfers
analogdevicesinc/hdl@c5b62a0 axi_dmac: fix 2d transfer address width
analogdevicesinc/hdl@e794d04 axi_dmac: renamed .h files to .vh
analogdevicesinc/hdl@7713738 axi_dmac: ttcl file support for simulation
analogdevicesinc/hdl@0d0989d axi_dmac: diagnostic interface in bursts
analogdevicesinc/hdl@7f4b6ca axi_dmac: Remove unused constraint
analogdevicesinc/hdl@e2c75c0 axi_dmac: add tlast to the axis interface for Intel
analogdevicesinc/hdl@8ddcffc axi_dmac: Enforce transfer length and stride alignments
analogdevicesinc/hdl@c4cb3df axi_dmac: Move transfer abort logic to data mover
analogdevicesinc/hdl@92984dc axi_dmac: Move sync transfer start logic to the data mover
analogdevicesinc/hdl@62969bd axi_dmac: Cleanup data mover
analogdevicesinc/hdl@44e09f5 axi_dmac: Remove backpressure from the source pipeline
analogdevicesinc/hdl@7d643e2 axi_dmac: Limit number of bursts on the source side
analogdevicesinc/hdl@d80175d axi_dmac: Remove second destination side register slice
analogdevicesinc/hdl@0d337ed axi_dmac: Eliminate beat counter for the destination interfaces
analogdevicesinc/hdl@71e14f6 axi_dmac: Route destination request ID through the burst memory
analogdevicesinc/hdl@859e3d2 axi_dmac: Rework data store-and-forward buffer
analogdevicesinc/hdl@fa99afc axi_dmac: dest_axi_mm: Simplify dependency management
analogdevicesinc/hdl@8c1d8e2 axi_dmac: Allow to disable FIFO interfaces immediately
analogdevicesinc/hdl@8937c36 axi_dmac: Hook up rlast for MM-AXI source interface
analogdevicesinc/hdl@8b272cf axi_dmac: Add testbenches that exercise DMA shutdown
analogdevicesinc/hdl@02bc91a axi_dmac: Rework transfer shutdown
analogdevicesinc/hdl@95c98c6 axi_dmac: Split transfer handling into separate sub-module
analogdevicesinc/hdl@751031e m2k:zed: Remove, as it's not part of the release
analogdevicesinc/hdl@80cfe26 axi_dmac: Be more specific about debug register timing exceptions
analogdevicesinc/hdl@80e7ba5 axi_dmac: Revert EOT memory to FIFO structure
analogdevicesinc/hdl@8b8df70 axi_dmac: request_generator: Remove reset from data path
analogdevicesinc/hdl@6bc1eae axi_dmac: 2d_transfer: Remove resets from data path
analogdevicesinc/hdl@6b7a464 axi_dmac: address_generator: Remove resets from data path
analogdevicesinc/hdl@67600f9 axi_dmac: Use localparam instead of parameter
analogdevicesinc/hdl@cf52081 axi_dmac: Increase default store-and-forward memory size to 8 bursts
analogdevicesinc/hdl@b18b16f axi_dmac: Use a more descriptive label for the store-and-forward memory size
analogdevicesinc/hdl@15b0e38 axi_dmac: List valid store-and-forward memory sizes
analogdevicesinc/hdl@682895c axi_dmac: dest_axi_stream: Remove outdated comment
analogdevicesinc/hdl@7a804c1 axi_dmac: Fix debug ID order
analogdevicesinc/hdl@3f94fec axi_dmac/dma_write_tb: added data integrity check
analogdevicesinc/hdl@5c2e10e axi_dmac: added ModelSim support to run_tb.sh
analogdevicesinc/hdl@ee4932e axi_dmac: made vlog pass
analogdevicesinc/hdl@24d17e8 axi_dmac: Add transfer testbenches
analogdevicesinc/hdl@b3f027f axi_dmac: Add simple register map testbench
analogdevicesinc/hdl@ef3687e axi_dmac: Split register map into separate sub-module
analogdevicesinc/hdl@ccb69e7 axi_dmac: axi_dmac_hw.tcl: Use ad_ip_files helper
analogdevicesinc/hdl@3cf33db axi_dmac: Fix bus resize block reset
analogdevicesinc/hdl@ee57f86 axi_dmac: Fix bus resize block reset

v0.22

M2k: prepare for v0.22

Changelog:

Submodule u-boot-xlnx f5f001e..89d0754:
  > configs: zynq_m2k_defconfig: Set bootldelay 0
  > board: xilinx: zynq: board: Optimize board_late_init

Signed-off-by: Michael Hennerich <[email protected]>

v0.21

M2k: prepare for v0.21

Changelog:

cc8b4ae Makefile: switch to arm-linux-gnueabihf toolchain found in the 2017.4 SDK
d07d777 Makefile: Build device tree for M2k HW Rev.D

Submodule buildroot f87e89f..1f06980:
  > board/m2k/post-build.sh: Add update firmware script
  > configs/zynq_m2k_defconfig: Switch to arm-linux-gnueabihf toolchain
  > board/pluto/update_frm: Add update firmware script
  > board/sidekiqz2/S23udc: Use proper EpiqSolutions USB VID 0x2FA2
  > Revert "sidekiqz2: use Pluto's msd data"
  > Merge pull request #5 from analogdevicesinc/sidekiqz2-symlink-pluto-msd
  > board/sidekiqz2/device_config: Fix FIRMWARE name

Submodule hdl 3cf33db..d79ca23:
  > daq3: ZCU102 project not supported in this release
  > adv7511:mitx045: Remove, as it's not part of the release
  > adv7511:ac701: Remove, as it's not part of the release
  > cn0363:microzed: Remove, as it's not part of the release
  > fmcomms2:mitx045: Remove, as it's not part of the release
  > m2k:zed: Remove, as it's not part of the release
  > imageon:zc706: Remove, as it's not part of the release
  > ad7768evb: Remove, as it's not part of the release
  > daq7980_sdz: Remove, as it's not part of the release
  > ad77681evb: Remove, as it's not part of the release
  > ad7616_sdz: Remove, as it's not part of the release
  > ad738x_fmc: Remove, as it's not part of the release
  > ad7134_fmc: Remove, as it's not part of the release
  > ad5766_sdz: Remove, as it's not part of the release
  > motcon2_fmc: Add additional clock constraints and set delays for ethernet
  > motcon2_fmc: Connect GPO pins to controller 1
  > motcon2_fmc: Sync transfer start for the current monitor DMAs
  > motcon2_fmc: Ethernet MDIO set to EMIO
  > motcon2_fmc: Update to revision C
  > axi_dacfifo: Always use equal or not equal
  > axi_dacfifo: Fix address buffer read logic
  > axi_dacfifo: Counters must use 1'b1 for incrementation
  > axi_dacfifo: Delete unused registers/nets
  > adrv9009: Throughput improvements
  > util_dacfifo_bypass: Update comments
  > _dacfifo: Fix the util_dacfifo_module
  > axi_dacfifo: Cosmetic changes in util_dacfifo_bypass
  > util_dacfifo: Fix gray coder/decoder
  > axi_dacfifo: Remove unused signals
  > axi_dacfifo: Add missing read-enable signal to ad_mem instance
  > daq3: ZCU102: Fix AXI_ADXCVR IPs XCVR_TYPE parameter
  > de10: Remove, as it's not supported in this release
  > fmcomms2: AC701: Remove, as it's not supported in this release
  > daq2|3: Set up OPTIMIZATION_MODE to improve timing
  > fmcjesdadc1: increase DMAC FIFO size
  > adrv9009: Removed ZC706 based project
  > adrv9009: Improved data throughput and DAC FIFO size

Submodule linux 105835a..83e5509:
  > arm: dts: add zynq-m2k Rev D,E,F device trees

Submodule u-boot-xlnx 73aff3d..f5f001e:
  > configs/zynq_sidekiqz2_defconfig: Use USB PID 0x5A32 in DFU mode
  > sidekiqz2: update u-boot env settings with manufacturer specs

Signed-off-by: Michael Hennerich <[email protected]>

v0.20

M2k: prepare for alpha - v0.20

Changelog:

065a6be legal_info_html.sh : Add BSD license, and tweak output to make it look like the other files on the mass storage device.
ce36d37 Makefile: Vivado use 2017.4
7ce2ee4 Makefile: Auto-generate LICENSE file

Submodule linux 7fbbe98..105835a:
  > iio: logic: m2k-fabric: Add support for DONE LED Overwrite (RevC)

Submodule buildroot a8fcddf..f87e89f:
  > html doc pages: Add placeholders & requests for translations which don't exist yet
  > html doc pages: add link to license at top, and fix locations of files which don't have translations yet.
  > style.css: Add a box with a border around it for the license
  > Merge pull request #4 from analogdevicesinc/buildroot-mtools
  > html doc pages: Add placeholders & requests for translations which don't exist yet
  > html doc pages: add link to license at top, and fix locations of files 	 which don't have translations yet.
  > style.css: Add a box with a border around it for the license
  > package/libiio: Bump to Version 0.15
  > Merge pull request #3 from analogdevicesinc/sidekiq-z2-support
  > board/m2k/genimage-msd.cfg: Use auto-generated License file
  > board/m2k/msd/.gitignore: Add ignore for autogenerated LICENSE file
  > board/pluto/busybox-1.25.0.config: Update config for busybox-1.27.2
  > Merge remote-tracking branch 'mainline/2018.02.x' into test-update
  > board/pluto/genimage-msd.cfg: Use auto-generated License file
  > board/m2k/m2k-calib.ini: Add default (none calibration file)

Submodule u-boot-xlnx efdb9e8..73aff3d:
  > Merge pull request #1 from analogdevicesinc/sidekiq-z2-support

Submodule hdl 944edeb...3cf33db:
  > axi_dmac: Fix bus resize block reset
  > Renamed ad9379 to adrv9009
  >  adrv9379:zcu102: Update to new revision of the board
  > adrv9379:zcu102: Move to FMC1
  > adrv9379:zcu102: Cleanup constraints
  > adrv9379:zcu102: Fix constraints, from ZCU102 rev B to ZCU102 rev D
  > adrv9379:ZCU102: Initial commit
  > axi_dmac: Limit MAX_BYTES_PER_BURST to maximum supported value
  > axi_dmac: axi_dmac_hw.tcl: Fix indention
  > axi_dmac: Prevent destination AXI burst length truncation
  > adi_ip.tcl: reorder synthesis files in the file group
  > Reviewed pinout of ZCU102 projects. fmcomms5 pin gpio_ad5355_lock location changed
  > axi_ad9162: Infer clock signal for tx_clk port
  > axi_dmac: adding missing dependency for Intel flow
  > axi_dmac: removed harmful SDC constraint
  > axi_dmac: AXI3 support on Intel qsys
  > fmcjesdadc1:a10: Move block design into feature branch
  > daq3: Connect the DAC data underflow
  > daq2: Connect the DAC data underflow
  > fmcomms5: Connect the DAC data underflow
  > fmcomms7: Move project to a feature branch
  > usdrx1: Move project to a feature branch
  > fmcomms2:pr: Move project to a feature branch
  > fmcomms11: Move project to a feature branch
  > fmcjesdadc1:altera: Move projects to a feature branch
  > daq1: Move project to a feature branch
  > usrpe31x: Delete deprecated project
  > adrv9364z7020:ccusb: Delete deprecated project
  > adrv9361z7035:ccusb: Delete deprecated project
  > adrv9361z7035:ccpci: Delete deprecated project
  > adv7511:kcu105: Delete deprecated project
  > adv7511:vc707: Delete deprecated project
  > adv7511:kc705: Delete deprecated project
  > ad_sysref_gen: Fix quartus warnings
  > ad_datafmt: Fix Quartus warnings
  > util_dacfifo: Fix Quartus warnings
  > quiet.mk: Fix newline generation in error message
  > de10: license: Fix a spelling mistake
  > axi_dmac: Disable 2D transfer support by default
  > axi_dmac: Remove unused pause signal from address generator
  > axi_dmac: Fix some indentation errors
  > jesd204: Update testbench with the new file names
  > jesd204: Fix file names
  > avl_dacfifo: Fix 'blocking statement in always block' issue
  > avl_dacfifo: Delete unused files
  > library: Remove empty constraint files
  > Add quiet mode to the Makefile system
  > axi_ad9144: Infer clock signal
  > axi_ad9250: Infer clock signals
  > Move Altera IP core dependency tracking to library Makefiles
  > library: Track additional file types as dependency in Makefile
  > axi_dmac_ip.tcl: Add include files to file list
  > util_dacfifo:  Infer clock and reset signals
  > axi_adcfifo: Infer clock and reset signals
  > library: Remove unreferenced files from IP file lists
  > project-*.mk Update CLEAN targets
  > Move Xilinx specific DC filter implementation to library/xilinx/common/
  > Makefile: Change IP component dependency to component definition file
  > Makefile: Don't create invalid sub-project targets
  > Makefile: Simplify sub-project target generation
  > Makefile: Update outdated example
  > Regenerate library Makefiles using the new shared Makefile include
  > Add common library Makefile
  > Regenerate project top-level Makefiles
  > Add shared project top-level Makefile
  > Regenerate project Makefiles using the new shared Makefile includes
  > Add common project Makefile for Xilinx projects
  > Add common project Makefile for Altera projects
  > Remove unused projects/common/Makefile
  > adrv9371x: Set up the defualt clock output control
  > ad77681evb: Add upscaler to the data path
  > adaq7980: Expouse the ADC sampling rate in system_bd.tcl
  > util_axis_fifo: instantiate block ram in async mode
  > daq3/kcu105: Define transceiver type as Ultrascale
  > DE10: Initial commit
  > sidekiqz2: Initial commit
  > adrv9371: Swap CSN lines to preserve consistency
  > ad_dcfilter: Enable output registers in DSP48E1
  > adrv9371x:zcu102: Use explicit PACKAGE_PIN definitions for JESD204 lanes and reference clocks
  > up_dac_common: Explicitly define boolean parameter as a 1 bit value
  > ad_xcvr_rx_if: rx_ip_sof_d register has a width of 4 bits
  > avl_dacfifo: Add missing wire declaration
  > avl_dacfifo: Delete deprecated false path definition
  > license: Fix a spelling mistake
  > license: Update old license headers
  > axi_hdmi_tx: removed unused registers
  > axi_adxcvr: Set the init value of the configuration registers
  > util_adxcvr: CPLLPD should be used for reset
  > axi_clkgen: Add a parameter to control the clock source options
  > adrv9371x:zcu102: Set DEVICE_TYPE to ultrascale
  > fmcadc2: Delete redundant settings
  > adi_xilinx_msg: eth_avb is not used by our designs
  > a10soc: Connect AXI register reset
  > util_adxcvr: Don't show reset ports for disabled lanes
  > util_[c|u]pack_dsf: clear syntehsis warnings
  > util_[w|r]fifo: Reduce synthesis warnings
  > up_delay_cntrl: Fix synthesis warnings, no functional changes
  > up_[adc|dac]_common: Define the DPR registers only when the interface is enabled
  > axi_dmac: fix synthesis warnings
  > adrv9379: Fix lane assignment, according to schematic
  > common: clean up synthesis warnings
  > axi_ad9361: clear synthesis warnings
  > adrv936x: Fix Ethernet
  > axi_dmac: Added MAX_BYTES_PER_BURST and  DISABLE_DEBUG_REGISTERS parameters to Intel IP
  > axi_hdmi_tx: Updated .sdc constraints
  > axi_hdmi_tx: Use abstract multiplier module supporting both Xilinx and Intel FPGAs
  > fmcomms2/zc702: Fix implementation timing issues
  > daq3: Add parameters for default xcvr configuration
  > daq2/fmcadc4/daq3: Disable the transfer start sync on the ADC DMA
  > axi_dmac: In SDP mode REGCEB is connected to GND
  > axi_ad7616: Add missing port to instantiation
  > spi_engine:axi_spi_engine: Add missing port to instantiations
  > axi_ad9963: Fix port dependency definition
  > ad738x_zed: Fix SCLK's pin assignment
  > ad738x: Add system variables for configuration
  > ad_tdd_control: Fix the tdd_burst_counter implementation
  > ad7134_fmc: Initial commit
  > util_axis_upscale: Initial commit
  > spi_engine: Add support for 8 SDI lines
  > util_pulse_gen: Use equal-to for counter reset
  > up_[adc|dac]_common: DRP_DISABLE should be boolean
  > constraints: up_xfer_cntrl and up_xfer_status have its own constraints
  > ad6676evb: Fix RX_DFE_LPM_CFG parameter, as the design is used in DFE mode
  > fmcadc5: Fix RXCDR_CFG parameter
  > fmcadc5: Remove xcvr configuration options that don't matter
  > axi_dacfifo: Rewrote constraints to be more specific
  > system_top: Non functional changes in system_tops to reduce warnings
  > axi_ad9434: Make adc_enable controllable from the channel register map
  > axi_*: Fix instantiation of up_[adc|dac]_[common|channel]
  > axi_*: Infer clock and reset signals of an IP
  > up_clock_com: Fix the false path definitions for CDCs
  > jesd_rst_gen:constraints: Remove invalid false path definitions
  > kc705/vc707/kcu105: Fix axi_spi related critical warning
  > axi_adcfifo_constr.xdc: Add missing backslash to command
  > axi_ad9162: Fix code alignment, no functional changes
  > base:constraint: Setting Configuration Bank Voltage Select
  > common/up_* : Make up_rstn synchronous to up_clk
  > scripts:adi_project: Update ZCU102 device package and board files
  > zcu102:all_projects: Delete required version tcl variable
  > scripts:adi_project: Use default strategies for synth and impl
  > scripts:adi_ip: Update web address format
  > scripts: Message severity changes on Vivado
  > scripts: Update tools for the next release
  > usb_fx3: Delete unused project
  > cftl: Delete unused projects and libraries
  > jesd204:tb: Fix the loopback_tb test bench
  > README: Remove the Documentation section, it's redundant
  > README: General rework and add more embedded links to wiki
  > README: A generic README update
  > axi_logic_analyzer: Fix push-pull/open-drain selection
  > Make: Use $(MAKE) for recursive make commands
  > Remove unused Q_OR_I_N parameter from JESD204 ADC cores
  > Remove unused IO_DELAY_GROUP parameter from JESD204 ADC cores
  > ad6676: Fix OUT_CLK_SEL configuration
  > fmcjesdadc1: Fix OUT_CLK_SEL configuration
  > fmcjesdadc1: Remove wire that is a redeclaration of a port
  > fmcomms5: Remove wires that are redeclarations of ports
  > axi_clkgen: add ultrascale series support
  > adrv9371x/kcu105: Use ultrascale type primitives in axi_clkgen IP
  > adrv9371x:kcu105: Update transceiver configuration
  > adrv9371x: kcu105: Fix transceiver and clock placement
  < axi_logic_analyzer: Fix push-pull/open-drain selection
  > Merge branch hdl_2017_r1


Signed-off-by: Michael Hennerich <[email protected]>

alpha - v0.19

M2k: prepare for alpha - v0.19

Changelog:

Submodule linux 5775bf4..7fbbe98:
  > iio: m2k-fabric: Don't update switch settings when they don't change

Submodule hdl bf3ba44..944edeb:
  > axi_logic_analyzer: Fix push-pull/open-drain selection

Submodule buildroot 72f3cd7..a8fcddf:
  > board/pluto/msd: Remove unused driver files
  > pluto, m2k: Add GPL2 LICENSE file to the MSD
  > Merge pull request #2 from analogdevicesinc/fix-flex-host-build
  > package/libad9361-iio: Fix typo in LICENSE_FILES
  > package/ad936x_ref_cal: Add LICENSE file and update

Signed-off-by: Michael Hennerich <[email protected]>

alpha - v0.18

M2k: prepare for alpha - v0.18

Changelog:

61fb064 Makefile: Build empty (cleanmarkers) jffs2 mtd2 dfu file

Submodule linux 8e78391..5775bf4:
  > zynq_m2k_defconfig: Enable JFFS2 support and disable use of 4k sectors

Submodule buildroot 6ae9f88..72f3cd7:
  > package: libad9361-iio: Add AD9361 library
  > package: libiio: Bump to Version 0.14
  > configs/zynq_[pluto|m2k]_defconfig: use compiler searched in $PATH
  > M2k: Implement mechanism to store and retrieve calibration data
  > board/pluto/update.sh: MTD layout allow 64k and 4k erase blocks
  > board/m2k/msd/img/index_fr|es.html: Fix download link
  > board/m2k/msd/index.html: Fix English and German HTML landing pages
  > board/pluto/S23udc: Add context attribute hw_model_variant

Submodule hdl 3e3955c..bf3ba44:
  > fmcomms11: Update the SPI IO definitions
  > fmcomms11: Update the clock tree
  > fmcomms11: Delete trailing whitespaces
  > axi_dmac: Include TLAST in AXIS slave port
  > axi_dmac: Add limited TLAST support for streaming AXI source interface
  > axi_ad9361: xilinx LVDS interface: Restore previous feedback clock polarity
  > ad9434: Specified DEVICE_TYPE parameter options
  > axi_ad9434.v Add description for parameter
  > axi_ad9434: Fix bad parameter definition
  > adrv9371: Increase FCLK2 to 200MHz to support max sampling rates

Signed-off-by: Michael Hennerich <[email protected]>

alpha - v0.17

M2k: prepare for alpha - v0.17

Submodule linux dbfd83f..8e78391:
  > drivers/mtd/spi-nor/spi-nor: Fix malicious locking support for n25qxxx
  > dts: zynq-m2k.dtsi: QSPI MTD add compatible n25q512a
  > m2k-fabric: Allow to update input and output configuration independenlty
  > iio: m2k-fabric: Remove unnecessary distinction between Rev C and non Rev C
  > iio: m2k-fabric: Remove Rev. B support
  > iio: m2k-fabric: Use same extended name for both NEG/POS supplies
  > dts: zynq-m2k-revc: Correct inverted pos and neg supply powerdown gpios

Submodule buildroot 0a4e137..6ae9f88:
  > package: libiio: Bump to version 0.12
  > package/libiio/libiio.mk: Push to version 0.11

Submodule u-boot-xlnx 9bc27b7..efdb9e8:
  > configs: zynq-common: Redo SF lock upon button press and failed boot

Submodule hdl 2b8adca...3e3955c:
  > avl_dacfifo: Fix avl_address generation
  > avl_dacfifo: Control the avl_burstcount inside the FSM
  > avl_dacfifo: Fix the last address buffer control
  > avl_dacfifo: dma_last_beats is transfered to avalon clock domain, without conditioning
  > daq2: Data underflow of DAC FIFO is monitored by the device core
  > avl_dacfifo: End of burst is not always end of a transaction
  > axi_streaming_dma_rx_fifo: fix period_count clock and TLAST
  > fmcadc5: Allow JESD reset from the ADC core, useful for synchronization
  > fmcadc5: Disable constraints for jesd sysref in order to remove critical warning
  > axi_dmac: Align the data_ready to data
  > daq2_zcu102: Fix typo
  > Require Vivado 2017.2.1 for all zcu102 projects
  > adrv9371x_zcu102: Fix rx_div_clk constraint placement
  > fmcadc5: Update make
  > fmcadc5: Update to the ADI JESD interface
  > Make: Update makefiles
  > library: Update
  > daq2, daq3: zcu102: Update constraints
  > daq2: Set correct transceiver type for UltraScale projects
  > adrv9371x: Set correct transceiver type for UltraScale projects
  > axi_adxcvr: Correctly report the transceiver type in the register map
  > adrv9371x: zcu102: Fix lane mapping
  > adrv9371x: zcu102: Fix QPLL feedback divider
  > fmcjesdadc1: Update A10GX/A10SOC projects to the ADI JESD framework
  > zcu102 constraints description/cosmetic updates
  > zcu102: Update to rev 1.0
  > fmcomms2: Connect dac data underflow
  > axi_dmac: Reset fifo_rd_data without delaying the valid data
  > avl_dacfifo: Fix dac_xfer_req generation
  > avl_dacfifo: Fix reset architecture in avl_dacfifo_rd
  > avl_dacfifo: Fix the loopback of avl_xfer_req
  > avl_dacfifo: Fix write enable generation
  > avl_dacfifo: Fix reset of write address register
  > daq3: Disable start synchronization for the ADC DMA
  > daq2: Disable start synchronization for the ADC DMA
  > avl_dacfifo: Refactor the fifo
  > daq2/zcu102: Pin Swap for ZCU102 Rev1.0
  > daq3: A10GX, overconstrained failing paths
  > daq3: A10GX, updated to the ADI JESD204
  > jesd204: Added additional input registers to jesd204_soft_pcs_rx, when lane rate is over 10Gbps
  > daq2: A10GX, added additional interconnect pipelining
  > adi_env: Normalize environment variables
  > adrv9371x: A10GX, added extra pipelining in the interconnect in order to improve timing
  > daq2: A10GX, added extra pipelining in the interconnect in order to improve timing
  > daq2: A10GX, connect dac_fifo_bypass to gpio
  > daq2: A10SOC, added dac fifo
  > daq2: A10GX, added dac fifo
  > axi_ad9361: Fix dac_datarate counter implementation
  > axi_dmac: Reset fifo_rd_data when DMA is off - v2
  > usdrx1/a10gx: Add external flash support
  > fmcjesdadc1/a10gx: Add external flash support
  > daq3/a10gx: Add external falsh support
  > adrv9371x/a10gx: Add external flash support
  > util_dacfifo: Integrate grey coder/decoder module
  > axi_dmac: Reset the fifo_rd_data if the DMA is off
  > a10gx: Force all used tiles to high speed, in order to improve timing
  > daq1_zed: Lower the adc and daq clock to 450MHz
  > arradio: Changed ADC DMA buswidth connection to the DDR to 128 bits
  > daq2/a10gx: Add cfi_flash to qsys
  > adrv9371x/a10soc: For receive paths SYNC_TRANSFER must be enabled
  > axi_ad9361: Fix incorrect merge
  > axi_dmac: Control s_axis_user/fifo_wr_sync validity
  > arradio: Fix the last incorrect merge
  > axi_dmac: Fix the last incorrect merge
  > axi_ad9361: Fix the last incorrect merge
  < adrv9361- inverted clock
  < axi_ad9361- allow clock inversion based on hardware
  < cftl: Delete unused projects and libraries
  < library- vivado 2017.2 update
  < daq1_zed: Lower the adc and daq clock to 450MHz
  > Merge branch 'dev' into hdl_2017_r1
  > A10GX: Update DDR3 configuration
  > license: Update old license headers
  > arradio: Changed ADC DMA buswidth connection to the DDR to 128 bits
  > axi_ad9361: Fix altera lvds interface, reverting to an older working version
  > arradio: Changed clock domain of the ADC and DAC path to half the interface clock
  > util_clkdiv: Added altera version
  > ad9361/xilinx- missing up_rstn
  > ZCU102: SPI assign chip selects individually
  > hdl/library- fix syntax errors/synthesis warnings
  > common: a10soc: Avoid unnecessary DMA clock domain crossing bridge insertion
  > up_clock_mon: Explicitly truncate d_count during up_d_count assignment
  > jesd204: jesd204_up_common: Rename clock monitor instance to i_clock_mon
  > jesd204: jesd204_up_ilas_mem: Fix blocking assignment
  > axi_dmac: axi_dmac_hw.tcl: Set read and write issuing capabilities
  > axi_dmac: axi_dmac_hw.tcl: Set default DMA_LENGTH_WIDTH to 24

Signed-off-by: Michael Hennerich <[email protected]>

alpha - v0.16

M2k: prepare for alpha - v0.16

Submodule linux 05dd68f..085bcdf:
  > iio: m2k-trigger-ad: Add streaming attribute
  > iio: m2k-trigger-ad: Add triggered attribute
  > iio: m2k-logic-analyzer: Add streaming attribute
  > iio: m2k-logic-analyzer: Add triggered attribute
  > iio: m2k-adc: Add calibration scale support
  > iio: m2k-dac: Add calibration scale support

Submodule buildroot 628b56c..0a4e137:
  > board/pluto/S23udc: Add fw_version context attribute
  > board/pluto/S23udc: strip leading "adi," from model contect attribute
  > board/pluto/S23udc: Add ad9361-phy,model context attribute

Submodule u-boot-xlnx 4bdff59..9bc27b7:
  > rsa: Fix build with OpenSSL 1.1.x

Submodule hdl c1e990b..2b8adca:
  > adrv9361- inverted clock
  > axi_ad9361- allow clock inversion based on hardware
  > cftl: Delete unused projects and libraries
  > library- vivado 2017.2 update
  > daq1_zed: Lower the adc and daq clock to 450MHz
  > interface: Update the transceiver interfaces
  > common/microzed: Enable PS CLK1 = 200MHz
  > common/a10soc: Update configuration for emif plddr4 IP
  > altera/ad_mem_asym: Delete it, QSYS flow is used
  > [axi|avl]_dacfifo: Create a separate bypass module for altera/xilinx
  > common/a10gx: Chance SPI frequency from 128KHz to 10 MHz
  > axi_adcfifo: Add missing constraints
  > adrv9379: Change the DMA clock to 250
  > arradio/c5soc- rd10102013_979 fix
  > adrv9371: a10soc: Whitespace cleanup
  > arradio- add control/status ports
  > arradio- add control/status ports
  > adrv9379: Initial commit
  > axi_ad9379: Initial commit
  > dm2k: Drive the ADC DMA valid from the trigger extracting core
  > axi_logic_analyzer: Compensate the 4 word latency of util_var_fifo
  > util_extract: Compensate 4 word latency
  > util_var_fifo: Set fix latency of 4 for all interpolation values
  > jesd204_rx: rx_ctrl: Fix typo
  > axi_ad9963: Moved RX configuration bit SCALECORRECTION_ONLY to bit 9
  > adrv9364/ccbox- input rf protection
  > adrv9361/ccbox- sort gpio - accidental multiple drivers
  > library- add a timer for quick start
  > adrv9361-ccbox/ccfmc- adl5904/gpio updates
  > adrv9361- add adl5904
  > adrv9371x: altera: Convert to ADI JESD204
  > altera: adi_jesd204: Export link domain reset
  > altera: adi_jesd204: Disable FPLL phase alignment mode
  > altera: adi_jesd204: Enable avmm_busy flag in the link FPLL register map
  > jesd204: jesd204_rx: Don't expose internal states on the status interface
  > axi_dmac: Better support debug IDs when ID_WIDTH != 3
  > adrv9371x_zcu102: Initial commit
  > adrv9371x_kcu105: Initial commit
  > adrv9371x/common: Remove ila_adc and ila_os_adc
  > adrv9371x/common: Fix axi_ad9371_dacfifo/dac_rst assignamen
  > adrv9371x: Separate ps7 assignaments from common
  > common/zcu102: Fix ps8 ref clock 0 frequency assignament
  > common/zcu102: Add gpio_t connections
  > avl_dacfifo: Update IP to qsys flow
  > adrv9371x: DAC_FIFO should get the dma_rst from sys_dma_rstgen
  > axi_dacfifo: Update constraints
  > fmcomms11: Connect data underflow to the core
  > axi_dacfifo: Major update and redesign
  > altera: jesd204_phy: Fix indention issues
  > daq2: Add support for Arria10 SoC platform
  > daq2: daq2_qsys.tcl: Convert to ADI JESD204
  > daq2: daq2_qsys.tcl: Rework peripheral addresses
  > library: Add ADI JESD204 wrapper for Altera/Intel platforms
  > library: Add JESD204 PHY wrapper for Arria10 Native PHY
  > jesd204: Add soft logic PCS
  > jesd204: Add Altera/Intel IP support
  > jesd204: jesd204_tx: Add dummy valid for the TX data interface
  > jesd204: ilas_mem: Rework to be more Altera friendly
  > util_cdc: Add helper function for creating constraints for the CDC blocks
  > adi_ip_alt.tcl: ad_ip_parameter: Allow to specify additional properties
  > adi_ip_alt.tcl: Allow to add TCL files to the fileset
  > jesd204: axi_jesd204_{rx,tx}: Add external link domain reset
  > util_adcfifo: Remove always false check
  > util_adcfifo: Fix data corruption at faster DMA clock rates
  > microzed: Add a secondary 200 MHz clock for PS7
  > axi_logic_anlayzer: Fix trigger AND logic
  > axi_streaming_dma_tx_fifo: Fix drain logic
  > axi_i2s_adi: Make constraints work on UltraScale
  > jesd204: axi_jesd204_rx_regmap_tb: Add missing dependency
  > axi_dmac: axi_dmac_hw.tcl: Set associated reset and addressable point for the interrupt interface
  > alt_mem_asym: Set read latency to 1 clock cycle
  > rfifo- drive valid outs
  > hdlmake.pl - updates
  > fmcomms2/zc702- pmod1 udc, pmod2 gpio
  > fmcomms5/zc702- pmods as gpios
  > adv7511/zc702- pmods as gpios
  > projects/zc702- free pmod gpio for customization
  > adrv936x- readme updates
  > adrv936x- readme updates
  > adrv936x- readme updates
  > Update README.md
  > util_adxcvr- defaults for es
  > hdlmake.pl- updates
  > jesd204: Use consistent naming scheme for CDC blocks
  > jesd204_tx: Use the CDC sync_bits helper to synchronize the SYNC~ signal
  > axi_jesd204_tx: Remove IRQ events for now
  > axi_jesd204_tx: jesd204_up_tx: Use two dimensional array for up_cfg_ilas_data
  > jesd204_tx: Remove duplicated file
  > jesd204: rx_tb: Fix some incorrect signal connections
  > axi_adxcvr: Avoid implicit signal truncation warning
  > common: a10soc: Use correct DDR memory reference clock type
  > ad9361- clkdiv to util_ad9361_divclk
  > fmcomms5- bd- data flow format
  > fmcadc2: Fix connection between a db port and a net
  > axi_ad9671: Fix typo
  > axi_ad9625: Fix typo
  > util_cdc: Update to verilog-2001 coding standard
  > util_axis_resize: Coding style updates
  > adrv936x- bd.tcl in data flow format
  > axi_ad9361: Update constraint file
  > ad738x_fmc: Supported sample rate is 3MSPS
  > ad738x_fmc: Configuration update/fix
  > spi_engine: Add support for max 4 SDI lines
  > ad738x_fmc: Initial commit
  > m2k: Move ADC hardware gain correction from the AD9963 IP to AXI_ADC_DECIMATE IP
  > axi_adc_decimate: Add correction at the end of the decimation chain
  > fmcomms2_bd- keep data flow format
  > common: a10soc: Mark external reset as asynchronous
  > avl_adxcvr: Perform octet order swap
  > avl_adxcvr: Simplify TX lane mapping
  > m2k: Enable correction for the interpolation module
  > axi_dac_interpolate: Add correction at the begining of the interpolation chain
  > axi_ad9361: Update the PPS receiver module
  > util_axis_fifo: Fix some data width mismatches
  > util_axis_fifo: Switch to Verilog-2001 style parameter declaration
  > axi_dmac: Set axi4lite address space size to 4k
  > axi_dmac: src_axi_stream: Terminate data mover m_axi_last signal
  > axi_dmac: axi_dmac_hw.tcl: Disable unused interfaces instead of not creating them
  > axi_dmac: dest_axi_mm: Use fixed wstrb signal
  > axi_dmac: Comment out unused src_response interface
  > axi_dmac: Fix some data width mismatches
  > library: Match s_axi_{awaddr,araddr} signal width to peripheral memory map size
  > util_upack: util_upack_hw.tcl: Disable unused interfaces instead of not creating them
  > util_cpack: util_cpack_hw.tcl: Disable unused interfaces instead of not creating them
  > axi_ad9144: axi_ad9144_hw.tcl: Disable unused interfaces instead of not creating them
  > axi_ad9144: Avoid implicit signal truncation warning
  > util_adcfifo: Avoid implicit signal truncation warning
  > axi_ad9680: axi_ad9680_hw.tcl: Fix typo
  > axi_adxcvr: Avoid warning about unknown synthesis attribute
  > adi_project_alt.tcl: Disable a few warnings generated by standard components


Signed-off-by: Michael Hennerich <[email protected]>

alpha - v0.15

M2k: prepare for alpha - v0.15

Submodule linux e4025f7..05dd68f:
  > drivers/iio/logic/m2k-fabric: Fix warning use cansleep variant
  > dts/zynq-m2k-rev[a|b].dts: m2k-fabric: Keep AMPs in powerdown after boot
  > iio/logic/m2k-fabric.c: Add clk_powerdown support
  > iio/logic/m2k-fabric: Add dt option to stay in PowerDown after boot
  > drivers/clk/clk-adf4360: Add PowerDown support

Submodule buildroot 6a099c7..628b56c:
  > configs/zynq_m2k_defconfig: check BR2_PACKAGE_LIBIIO
  > Merge branch 'pluto' of https://github.com/analogdevicesinc/buildroot into pluto
  > board/m2k/S16xadc: Keep XADC around for now
  > board/m2k/S21misc: PowerDown M2K clocks after boot
  > board/pluto/S23udc: Add ad9361-phy,xo_correction context attribute
  > configs/zynq_m2k_defconfig: Add LIBIIO_IIOD_USBD
  > configs/zynq_pluto_defconfig: Add LIBIIO_IIOD_USBD
  > package/expat/expat: Downgrade to version 2.2.0
  > Revert "skeleton: fix permissions on /dev/pts/ptmx"
  > Merge remote-tracking branch 'origin/pluto' into test
  > Merge tag '2017.05.1' into test

Submodule hdl 99e8aa3..c1e990b:
  > ad9361/sw- current sw requires clock edge swap
  > adrv9364- ps_intr_11 used for pps
  > library/ad9361- gps_pps default value
  > projects/ remove upack dma_xfer_in
  > library/ad9361- add pps module
  > hdlmake.pl updates
  > adrv9361x/- ps_intr_11 used for pps
  > daq3/zcu102: Initial commit
  > daq1_zed: Initial commit
  > arradio- remove dma_xfer_in from upack
  > rfifo/upack- changes
  > util_upack- port updates
  > ad_mem- syntax error fix
  > util_rfifo- add valid turnaround
  > util_upack- add valid turnaround
  > Remove executable flag from non-executable files
  > avl_adxcvr: Derive PLL and core clock frequency from lane rate
  > avl_adxcvr: Fix core clock bridge frequency
  > common: a10soc: Set IO standard for differential signal negative side
  > common: a10soc: Fix gpio_bd_i constraints
  > license: Update old license headers
  > adrv9364z7020: Connect the gps_pps signal to the receiver
  > adrv9361z7035: Connect the gps_pps signal to the receiver
  > axi_ad9361: ad_pps_receiver integration
  > ad_pps_receiver: Initial commit
  > A10GX: Update DDR3 configuration
  > jesd204: axi_jesd204_rx_regmap_tb: Check ILAS memory register
  > hdlmake.pl- remove ad_lvds
  > library & projects- ad_lvds/ad_data replace
  > library- remove ad_cmos_*
  > ad77681evb/zed: ad_lvds-ad_data replace
  > ad9361/xilinx/lvds_if- fix frame check
  > library/xilinx/common- add iodelay group
  > hdlmake.pl/fmcomms2- updates
  > axi_ad9361- altera/xilinx reconcile- may be broken- do not use
  > library/xilinx- lvds/cmos integration
  > fmcomms2_kcu105: Initial commit
  > axi_dmac: axi_dmac_hw.tcl: Automatically detect clock domains
  > axi_dmac: axi_dmac_hw.tcl: Cleanup configuration parameters
  > avl_adxcfg: Consistently use non-blocking assignments
  > library: Use ad_ip_intf_s_axi were applicable
  > adi_ip_alt.tcl: ad_ip_intf_s_axi: Allow to specify AXI interface address width
  > altera: axi_adxcvr: Reduce register map interface address width
  > hdlmake.pl updates
  > axi_ad9361/altera- add 10 support
  > ad9361/xilinx- missing up_rstn
  > Partially revert "hdlmake.pl - updates"
  > axi_dac_interpolate: Added matlab file for interpolation filters
  > axi_adc_decimate: Added matlab file for filters
  > ZCU102: SPI assign chip selects individually
  > hdlmake.pl - updates
  > arradio- timing violations fix
  > altera- remove lvds/serdes/cmos cores
  > alt_serdes- remove c5 support
  > library- remove c5 cores
  > hdl/library- fix syntax errors/synthesis warnings
  > common: a10soc: Avoid unnecessary DMA clock domain crossing bridge insertion
  > up_clock_mon: Explicitly truncate d_count during up_d_count assignment
  > jesd204: jesd204_up_common: Rename clock monitor instance to i_clock_mon
  > jesd204: jesd204_up_ilas_mem: Fix blocking assignment
  > axi_dmac: axi_dmac_hw.tcl: Set read and write issuing capabilities
  > axi_dmac: axi_dmac_hw.tcl: Set default DMA_LENGTH_WIDTH to 24
  > arradio/c5soc- clocking changes
  > arradio/c5soc- interface updates
  > arradio/c5soc- interface updates
  > rfsom2/ccbox- rtc int
  > rfsom/ccbox- rtc int
  > rfsom2/ccbox- tsw s5 fix
  > rfsom2/ccbox- tsw updates
  > rfsom/ccbox- tsw updates
  > daq2: daq2_qsys.tcl: Use sys_dma_clk
  > jesd204: tx_ctrl: Fix status_sync assignment
  > jesd204: jesd204_up_sysref: Remove unused signals
  > jesd204: jesd204_up_common: Add missing core_cfg_transfer_en declaration
  > jesd204: axi_jesd204_up_rx_lane: Fix padding signal width
  > jesd204: Add names for generate for-blocks
  > axi_dmac: request_arb: Add missing req_gen_{valid,ready} signal declaration
  > axi_dmac: Update to verilog-2001 coding style
  > axi_dacfifo: Fix port width at axi_dacfifo_wr
  > adrv9371x: Write parameter as hexa value to clear Vivados ambiguity between decimal and binary
  > jesd204: Update constraints for tx register map
  > daq3/zc706: Fix system_top instantiation
  > axi_xcvrlb: Fix util_adxcvr_xch instantiation (6d4430)
  > axi_dacfifo: Fix axi_dlast generation
  > axi_dacfifo: Few cosmetic changes
  > axi_dacfifo: Increase the width of axi_last_beats and wvalid_counter
  > plddr3_dacfifo_bd: Increase the AXI burst length to max
  > axi_dacfifo: Define DMA/DAC_MEM_ADDRESS as parameter
  > axi_dacfifo: DAC side CDC fifo control update
  > axi_dacfifo: Add gray coder/decoder module
  > ad_axis_inf_rx: Delete redundant local paramter
  > axi_dacfifo: Fix the dma_ready signal generation
  > fmcjesdadc1: vc707: Remove unsed mb_intrs signal
  > Connect JESD204 interrupts
  > axi_logic_analyzer: Streaming flag initial commit

Signed-off-by: Michael Hennerich <[email protected]>

alpha - v0.14

M2k: prepare for alpha - v0.14

Add support for ADALM-2000 M2k Hardware Rev.B

Submodule linux 751f62f..e4025f7:
  > configs/zynq_m2k_defconfig: Extend wired USB Ethernet device support
  > arch/arm/boot/dts/zynq-m2k-revb.dts: Also remove the AD7291 supply mon
  > arch/arm/boot/dts/zynq-m2k-reva.dts: Fix ADF4360 LD GPIO assignment
  > arch/arm/boot/dts/zynq-m2k-reva.dts: Fix 5V0_A Regulator
  > arch/arm/boot/dts/zynq-m2k-revb.dts: Add support for M2k Hardware RevB
  > arch/arm/configs/zynq_m2k_defconfig: Update add USB ETH support
  > iio: ad_adc: Add calibration scale support to the M2K ADC
  > iio: m2k-logic-analyzer: Add support for positive trigger delay
  > iio: m2k-logic-analyzer: Add support for configuring clock source
  > iio: m2k-logic-analyzer: Add support for configuring output mode
  > iio: m2k adc trigger: Add support for positive trigger delay

Submodule buildroot 50c07c5..6a099c7:
  > package/libiio/libiio.mk: Conditionally add dependency to libini
  > zynq_m2k_defconfig: Make sure libiio is build with WITH_LOCAL_CONFIG
  > Merge branch 'pluto' of https://github.com/analogdevicesinc/buildroot into pluto
  > zynq_pluto_defconfig: Make sure libiio is build with WITH_LOCAL_CONFIG
  > board/pluto: Add support for Wired Ethernet using a USB Ethernet adapters
  > package/libiio/libiio.mk: Update to Version 0.10
  > package/poll_sysfs/Config.in: Fix poll sysfs inclusion
  > board/pluto/update: config.txt add udc_handle_suspend
  > board/pluto/update.sh: Add ref clock calibration support via config.txt
  > board/pluto/S21misc: Add support for none volatile user set XO Correction
  > configs/zynq_pluto_defconfig: Enable package POLLSYSFS, AD936x_REF_CAL
  > board/pluto/udc_handle_suspend: Add UDC suspend script
  > package/ad936x_ref_cal: Add reference clock calibration utility for AD936x
  > package/poll_sysfs: Add SYSFS POLL utility
  > package/libiio/libiio.mk: Update libiio to 60063cb
  > board/pluto/S40network: Be less verbose
  > package/libiio/libiio.mk: Update to 34933f1a6419e6c0be46a64b039f6c85646172d9
  > board/pluto/S45msd: Patch foreign language HTML pages as well
  > board/pluto/msd/index.html: Fix subpage links and fix typo
  > board/pluto/msd: Move foreign language HTML pages to the img dir
  > board/pluto/msd/img/index_de.html: Add German HTML Welcome page
  > Pluto doc: Fix links to Spanish index page
  > Pluto doc: Add a Spanish page
  > Pluto doc: some tweaks to the French page
  > Pluto doc: Add a French page
  > Pluto doc: fix typo
  > board/pluto/S21misc: increase max_block_size to 64M
  > Pluto index: 	add safety requirements
  > Update page on mass storage

Submodule hdl 7cff121..99e8aa3:
  > axi_adc_trigger Streaming flag initial commit
  > axi_adc_trigger: Fix triggered flag
  > axi_logic_analyzer: Fixed triggered flag
  > daq3: Provide DAC JESD204 lane mapping
  > kc705: Fix ethernet address span
  > arradio: Add i2c interface
  > axi_logic_analyzer: Fix direction change in non-streaming mode
  > util_adxcvr: Bring back channel 8
  > axi_adxcvr/util_adxcvr: Fix non-broadcast DRP access
  > common: Delete deprecated modules
  > make: Update make files
  > axi_ad9652: Remove deprecated IP
  > axi_ad9643: Remove deprecated IP
  > axi_ad9234: Remove deprecated IP
  > common: Remove deprecated modules
  > util_ccat: Remove deprecated IP
  > axi_logic_analyzer: Added triggered flag
  > axi_adc_trigger: added triggered flag
  > ad77681evb: Suppress a critical warning
  > adrv9371_alt: Delete the fifos from the RX path
  > library/avl_adxcvr: fpll fixes
  > jesd204: tb: Fix signal width mismatch warnings
  > jesd204: rx_static_config: Set RBD to 0
  > jesd204: rx: Use standalone counter for lane latency monitor
  > jesd204: Handle sysref events in the register map
  > jesd204: Properly align LMFC offset in register map
  > jesd204: Slightly rework sysref handling
  > library: jesd204: jesd204_up_common: Fix indention
  > daq2: Provide DAC lane map
  > adi_board.tcl: ad_xcvrcon: Add lane mapping support
  > up_clock_mon: Fix stopped clock detection logic
  > axi_ad5766: Delete unused interface definition
  > axi_logic_analyzer: Fix delayed trigger assertion condition
  > util_clkdiv: Register output port as a clock (#33)
  > jesd204- apply constraints after top
  > adi_ip.tcl- general rule- order independent constraints
  > daq3- updated to 12.5G
  > fmcjesdadc1/a10gx- fix sysref, lvds io and such
  > fmcjesdadc1/a10soc- fix sysref, lvds io and such
  > hdlmake.pl updates
  > a5gt/a5soc - removed
  > a5gt/a5soc - removed
  > adi_ip_alt: allow composition only parameter settings
  > avl_adxcvr: remove arria v support
  > hdlmake.pl updates
  > usdrx1/a10gx- updated to a10gx
  > usdrx1/a10gx- added
  > fmcjesdadc1/a10soc- sysref fixes
  > fmcjesdadc1/a10gx- fix sysref, gpio connections
  > hdlmake.pl updates
  > fmcjesdadc1: a10gx/a10soc
  > fmcjesdadc1: a10gx/a10soc
  > fmcjesdadc1: a10soc
  > fmcjesdadc1: a10gx
  > hdlmake.pl- updates
  > scripts- add a5soc device
  > common/a5soc- alt 16.1 updates
  > fmcjesdadc1/a5soc- alt 16.1 updates
  > axi_gpreg: Fixed constraints
  > hdlmake.pl updates
  > altera- altera ip interfaces has no consistency
  > fmcjesdadc1/a5gt- altera 16.1 updates
  > common/a5gt- altera 16.1 updates
  > scripts/adi_project_alt- add a5soc, a5gt
  > alt_ifconv-- qsys workaround
  > altera 16.1 c5soc updates
  > altera 16.1 arradio updates
  > adi_project_alt: add c5soc
  > altera 16.1- recommends using fpll for dedicated low skew clock routing
  > axi_logic_analyzer: Update triggering delay mechanism
  > axi_adc_trigger: Update triggering delay mechanism
  > hdlmake.pl - updates
  > daq3/a10gx- alt 16.1 updates
  > adrv9371x/a10gx- alt 16.1 updates
  > ad77681evb: Fix IO constraints
  > avl_dacfifo: Fix timing violation
  > scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects
  > hdlmake.pl- updates
  > daq2/a10gx- project/constraint updates
  > hdlmake.pl - updates
  > common/a10soc- add project create tcl procedure
  > adrv9371x/a10soc- constraints/project updates
  > adrv9371x/a10gx-  constraints/project updates
  > altera- 16.1.2 & a10soc
  > up_clock_mon- name changes
  > util_fir_int: Fix valid assignment
  > adrv9371x:a10gx, update create project command and Makefile
  > scripts: changed adi_project_create command to adi_project_altera
  > m2k: Updated project to work with the fifo_depth related changes
  > axi_logic_analyzer: Added trigger delay register, renamed fifo depth register
  > axi_adc_trigger: Added trigger delay register, renamed fifo depth register
  > make: Update make files
  > adrv9364z7020- fix enable/en_agc mixup
  > altera- remove default assignments from procedure
  > altera- adi-project-create version
  > adi_project- altera version
  > adi_ip- initialize xdc list when ip is created
  > jesd204-sub-ip- no top files
  > Merge branch 'jesd204' into dev
  > axi_ad9963: Delete unused source from *_ip.tcl
  > license: Add some clarification to the header license
  > license: GPL must be GPL v2
  > util_extract: Estetic changes
  > altera- 2017-r1 16.1.2
  > util_extract: Update parameter names
  > license: Add few cosmetic changes to LICENSE
  > license: Update top level LICENSE file
  > license: Add top level license files
  > license: Update license terms in hdl source files
  > alt_serdes- 16.1 updates
  > library: move alt cores to common
  > altera 16.1 ip changes
  > altera 16.1 ip changes
  > fmcomms2/a10gx: Remove project
  > daq1/a10gx: Remove project
  > m2k: Fix Make files
  > adrv9364z7020: Update README
  > adrv9361z7035: Update README
  > adrv9364z7020: Rename pzsdr1 to adrv9364z7020
  > adrv9361z7035: Rename pzsdr2 to adrv9361z7035
  > make: Update make files
  > constraints: Split the regmap CDC constraint into separate file
  > avl_dacfifo: Update constraints
  > avl_dacfifo: Cosmetic changes
  > avl_dacfifo: Fix issues with avl_dacfifo_wr
  > avl_dacfifo: Add support for partial avalon transfers
  > avl_dacfifo: Grey coder/decoder integration
  > common: Add grey coder and decoder modules
  > avl_dacfifo: Add avl_dacfifo_byteenable_coder
  > avl_dacfifo: Few cosmetic changes on avl_dacfifo_wr
  > avl_dacfifo: Add support for MEM_RATIO 32
  > avl_dacfifo: Integrate util_delay into dac_xfer_out path
  > avl_dacfifo: dma_ready was muxed incorrectly
  > avl_dacfifo: Fix the avalon address switch
  > avl_dacfifo: Fix a few control signals
  > avl_dacfifo: Fix the avl_write generation
  > avl_dacfifo: Fix alv_mem_readen generation
  > avl_dacfifo: Few cosmetic changes on avl_dacfifo_wr
  > util_delay: Initial commit
  > avl_dacfifo: Fix indentation for acl_dacfifo.v
  > avl_dacfifo: Add a parameter AVL_ADDRESS_WIDTH
  > altera/ad_mem_asym: Fix grounded bus for marco instance
  > adi_ip.tcl: Use analog.com for interface vendor
  > interfaces: Add dependencies to rule
  > interfaces: Simplify Makefile
  > m2k: Add scale correction option. Update parameters
  > axi_ad9963: Add scale only correction option
  > ad_iqcor: Add scale only correction option
  > pzsdr2/ccfmc: enable eth1 mdio
  > usdrx1- spi/mlo fixes
  > motcon2_fmc: Explicitly assign ETH0 MDIO to EMIO
  > axi_hdmi_rx- move data to an iob
  > fmcadc2/vc707- spi clock reg can't be on iob
  > daq3/kcu105- reorder refclk constraints
  > kcu105- vivado now depends on order of constraints?
  > kcu105- remove ethernet delay ctrl false path
  > library: Sort Makefile
  > m2k: Refresh Makefile
  > util_adxcvr- 2016.4 gthe4 updates
  > zcu102- 2016.4 updates
  > adrv9371x fix dacfifo name
  > quartus optimization for frequency
  > alt_mul- qsys replacement
  > alt-jesd- constraints update
  > a10soc- 16.1- hsp sdram reset
  > a10soc- fix version check
  > resolving conflicts
  > alt-mem-asym - replace mega function cores
  > adi-ip-alt allow changing device family
  > alt_mem_asym- qsys component
  > license: Fix VHDL license header
  > scripts: Update required tool versions
  > Fix VHDL files license header, second try
  > Fix VHDL files license header
  > axi_usb_fx3: Add missing ports
  > all: Update license for all hdl source files
  > util_fir_int: Force 1/8 filter input data rate
  > axi_adc_decimate/cic_decim: Fix clk_enable warning
  > util_tdd_sync: add missing ports
  > Remove duplicare wire declaration
  > Add missing ad_serdes_out interface ports
  > daq2/a10gx- constraints remove 16.0
  > axi_ad9963: Update constraints as adc_common and dac_common paths have been renamed
  > up_dac_common: rename internal signals
  > a10gx- change ddr to 1G
  > altera- add version check
  > altera- infer latest versions
  > altera- default to latest version
  > version check- change to critical warning
  > axi adc cores: Add missing ports to up_adc_common instance
  > axi dac cores: Add missing ports to up_dac_common instance
  > fmcadc5-sync: added a convenience timer
  > axi_ad5766: Add missing ports to up_dac_common instance
  > axi_ad5766: sdo_mem size is 3
  > axi_ad5766: Delete redundant parameters
  > axi_generic_adc: Update port names for up_adc_common instance
  > fmcadc5- syntax/port name fixes
  > up_adc_common- port name changes
  > hdlmake.pl updates
  > axi_fmcadc5- remove pack-driver is too late
  > axi_fmcadc5- sign-extend and interleave (core is too late)
  > ad9625- add an option to control cs monitoring
  > library/up_adc_common- add sref sync option
  > library/axi_fmcadc5_sync- remove dependecy on adc-core (driver shows up late)
  > axi_ad9739a: Fix DDS set frequency
  > axi_ad9371: Update dac_clk_ratio to 2
  > axi_fmcadc5_sync- raw inputs & constraint fixes
  > axi_fmcadc5_sync- raw inputs & constraint fixes
  > hdlmake.pl updates
  > axi_fmcadc5_sync- calcor added
  > axi_ad9434: Fix input data rate
  > ad77681evb: Initial commit
  > spi_engine_offload: Add a CDC module for trigger reception
  > spi_engine: Define parameter inside the module statement
  > adrv9371x/a10soc: Fix constraints
  > zcu102: Automatic IP version update fix
  > zcu102: Automatic IP version update
  > usrpe31x: Automatic IP version update
  > pzsdr*: Automatic IP version update
  > change pl ddr clock to 1G
  > axi_fmcadc5_sync: add a calibration signal generation
  > daq2: zc706: Increase DAC FIFO size
  > adaq7980: Update tcl command for IP configuration
  > ad5766_sdz: Update tcl commands for IP configuration
  > hdlmake- updates
  > fmcadc5- remove stand alone psync
  > fmcadc5- remove psync module
  > adi_boadr- disconnect and remove unused ports
  > fmcadc5- sync updates
  > fmcadc5-sync- add ldo psync
  > util_adxcvr: Fix parameter setup at instantiation
  > axi_ad5766: Fix parameter name for up_dac_common
  > ad5766_sdz/zed: Fix i_iobuf_reset width
  > spi_engine_interconnect: Delete dependency defined for S1_CTRL interface
  > util_pulse_gen: Add Makefile
  > adaq7980/zed: Update Makefile
  > spi_engine: Expose DATA_WIDTH to software
  > util_pulse_gen: The valid period is stored in pulse_period_d
  > adaq7980: Add an trigger generator for SPI offload
  > adaq7980_sdz: Initial commit
  > spi_engine_execution: Define port dependencies for SDI ports
  > axi_spi_engine: Define ports dependencies for up_* interface
  > ad5766_sdz: Fix the PIN assignment
  > cn0363: Update block design
  > up_dac_common: Increase datawidth of dac_datarate
  > ad5766_sdz: Fix DMA data path
  > axi_ad5766: Add Makefiles for the core
  > axi_ad5766: Preserve consistent coding style
  > ad5766_zed: Add an IOBUF to the reset line
  > ad5766: Integrate the new axi_ad5766 into the project
  > util_pulse_gen: Add configuration interface for 'pulse period'.
  > interface: Update spi_engine_offload_ctrl definition
  > spi_engine: Fix CMD_FIFO_VALID generation
  > axi_ad5766: Initial commit
  > ad5766_sdz : Fix SPI interface connection
  > spi_engine: Add dependency for unused interfaces
  > ad5766_sdz: Initial commit
  > ad9162- add iq swap
  > axi_ad9361: Fix ad_cmos_out instantiations


Signed-off-by: Michael Hennerich <[email protected]>