M2k: prepare for alpha - v0.14
Add support for ADALM-2000 M2k Hardware Rev.B
Submodule linux 751f62f..e4025f7:
> configs/zynq_m2k_defconfig: Extend wired USB Ethernet device support
> arch/arm/boot/dts/zynq-m2k-revb.dts: Also remove the AD7291 supply mon
> arch/arm/boot/dts/zynq-m2k-reva.dts: Fix ADF4360 LD GPIO assignment
> arch/arm/boot/dts/zynq-m2k-reva.dts: Fix 5V0_A Regulator
> arch/arm/boot/dts/zynq-m2k-revb.dts: Add support for M2k Hardware RevB
> arch/arm/configs/zynq_m2k_defconfig: Update add USB ETH support
> iio: ad_adc: Add calibration scale support to the M2K ADC
> iio: m2k-logic-analyzer: Add support for positive trigger delay
> iio: m2k-logic-analyzer: Add support for configuring clock source
> iio: m2k-logic-analyzer: Add support for configuring output mode
> iio: m2k adc trigger: Add support for positive trigger delay
Submodule buildroot 50c07c5..6a099c7:
> package/libiio/libiio.mk: Conditionally add dependency to libini
> zynq_m2k_defconfig: Make sure libiio is build with WITH_LOCAL_CONFIG
> Merge branch 'pluto' of https://github.com/analogdevicesinc/buildroot into pluto
> zynq_pluto_defconfig: Make sure libiio is build with WITH_LOCAL_CONFIG
> board/pluto: Add support for Wired Ethernet using a USB Ethernet adapters
> package/libiio/libiio.mk: Update to Version 0.10
> package/poll_sysfs/Config.in: Fix poll sysfs inclusion
> board/pluto/update: config.txt add udc_handle_suspend
> board/pluto/update.sh: Add ref clock calibration support via config.txt
> board/pluto/S21misc: Add support for none volatile user set XO Correction
> configs/zynq_pluto_defconfig: Enable package POLLSYSFS, AD936x_REF_CAL
> board/pluto/udc_handle_suspend: Add UDC suspend script
> package/ad936x_ref_cal: Add reference clock calibration utility for AD936x
> package/poll_sysfs: Add SYSFS POLL utility
> package/libiio/libiio.mk: Update libiio to 60063cb
> board/pluto/S40network: Be less verbose
> package/libiio/libiio.mk: Update to 34933f1a6419e6c0be46a64b039f6c85646172d9
> board/pluto/S45msd: Patch foreign language HTML pages as well
> board/pluto/msd/index.html: Fix subpage links and fix typo
> board/pluto/msd: Move foreign language HTML pages to the img dir
> board/pluto/msd/img/index_de.html: Add German HTML Welcome page
> Pluto doc: Fix links to Spanish index page
> Pluto doc: Add a Spanish page
> Pluto doc: some tweaks to the French page
> Pluto doc: Add a French page
> Pluto doc: fix typo
> board/pluto/S21misc: increase max_block_size to 64M
> Pluto index: add safety requirements
> Update page on mass storage
Submodule hdl 7cff121..99e8aa3:
> axi_adc_trigger Streaming flag initial commit
> axi_adc_trigger: Fix triggered flag
> axi_logic_analyzer: Fixed triggered flag
> daq3: Provide DAC JESD204 lane mapping
> kc705: Fix ethernet address span
> arradio: Add i2c interface
> axi_logic_analyzer: Fix direction change in non-streaming mode
> util_adxcvr: Bring back channel 8
> axi_adxcvr/util_adxcvr: Fix non-broadcast DRP access
> common: Delete deprecated modules
> make: Update make files
> axi_ad9652: Remove deprecated IP
> axi_ad9643: Remove deprecated IP
> axi_ad9234: Remove deprecated IP
> common: Remove deprecated modules
> util_ccat: Remove deprecated IP
> axi_logic_analyzer: Added triggered flag
> axi_adc_trigger: added triggered flag
> ad77681evb: Suppress a critical warning
> adrv9371_alt: Delete the fifos from the RX path
> library/avl_adxcvr: fpll fixes
> jesd204: tb: Fix signal width mismatch warnings
> jesd204: rx_static_config: Set RBD to 0
> jesd204: rx: Use standalone counter for lane latency monitor
> jesd204: Handle sysref events in the register map
> jesd204: Properly align LMFC offset in register map
> jesd204: Slightly rework sysref handling
> library: jesd204: jesd204_up_common: Fix indention
> daq2: Provide DAC lane map
> adi_board.tcl: ad_xcvrcon: Add lane mapping support
> up_clock_mon: Fix stopped clock detection logic
> axi_ad5766: Delete unused interface definition
> axi_logic_analyzer: Fix delayed trigger assertion condition
> util_clkdiv: Register output port as a clock (#33)
> jesd204- apply constraints after top
> adi_ip.tcl- general rule- order independent constraints
> daq3- updated to 12.5G
> fmcjesdadc1/a10gx- fix sysref, lvds io and such
> fmcjesdadc1/a10soc- fix sysref, lvds io and such
> hdlmake.pl updates
> a5gt/a5soc - removed
> a5gt/a5soc - removed
> adi_ip_alt: allow composition only parameter settings
> avl_adxcvr: remove arria v support
> hdlmake.pl updates
> usdrx1/a10gx- updated to a10gx
> usdrx1/a10gx- added
> fmcjesdadc1/a10soc- sysref fixes
> fmcjesdadc1/a10gx- fix sysref, gpio connections
> hdlmake.pl updates
> fmcjesdadc1: a10gx/a10soc
> fmcjesdadc1: a10gx/a10soc
> fmcjesdadc1: a10soc
> fmcjesdadc1: a10gx
> hdlmake.pl- updates
> scripts- add a5soc device
> common/a5soc- alt 16.1 updates
> fmcjesdadc1/a5soc- alt 16.1 updates
> axi_gpreg: Fixed constraints
> hdlmake.pl updates
> altera- altera ip interfaces has no consistency
> fmcjesdadc1/a5gt- altera 16.1 updates
> common/a5gt- altera 16.1 updates
> scripts/adi_project_alt- add a5soc, a5gt
> alt_ifconv-- qsys workaround
> altera 16.1 c5soc updates
> altera 16.1 arradio updates
> adi_project_alt: add c5soc
> altera 16.1- recommends using fpll for dedicated low skew clock routing
> axi_logic_analyzer: Update triggering delay mechanism
> axi_adc_trigger: Update triggering delay mechanism
> hdlmake.pl - updates
> daq3/a10gx- alt 16.1 updates
> adrv9371x/a10gx- alt 16.1 updates
> ad77681evb: Fix IO constraints
> avl_dacfifo: Fix timing violation
> scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects
> hdlmake.pl- updates
> daq2/a10gx- project/constraint updates
> hdlmake.pl - updates
> common/a10soc- add project create tcl procedure
> adrv9371x/a10soc- constraints/project updates
> adrv9371x/a10gx- constraints/project updates
> altera- 16.1.2 & a10soc
> up_clock_mon- name changes
> util_fir_int: Fix valid assignment
> adrv9371x:a10gx, update create project command and Makefile
> scripts: changed adi_project_create command to adi_project_altera
> m2k: Updated project to work with the fifo_depth related changes
> axi_logic_analyzer: Added trigger delay register, renamed fifo depth register
> axi_adc_trigger: Added trigger delay register, renamed fifo depth register
> make: Update make files
> adrv9364z7020- fix enable/en_agc mixup
> altera- remove default assignments from procedure
> altera- adi-project-create version
> adi_project- altera version
> adi_ip- initialize xdc list when ip is created
> jesd204-sub-ip- no top files
> Merge branch 'jesd204' into dev
> axi_ad9963: Delete unused source from *_ip.tcl
> license: Add some clarification to the header license
> license: GPL must be GPL v2
> util_extract: Estetic changes
> altera- 2017-r1 16.1.2
> util_extract: Update parameter names
> license: Add few cosmetic changes to LICENSE
> license: Update top level LICENSE file
> license: Add top level license files
> license: Update license terms in hdl source files
> alt_serdes- 16.1 updates
> library: move alt cores to common
> altera 16.1 ip changes
> altera 16.1 ip changes
> fmcomms2/a10gx: Remove project
> daq1/a10gx: Remove project
> m2k: Fix Make files
> adrv9364z7020: Update README
> adrv9361z7035: Update README
> adrv9364z7020: Rename pzsdr1 to adrv9364z7020
> adrv9361z7035: Rename pzsdr2 to adrv9361z7035
> make: Update make files
> constraints: Split the regmap CDC constraint into separate file
> avl_dacfifo: Update constraints
> avl_dacfifo: Cosmetic changes
> avl_dacfifo: Fix issues with avl_dacfifo_wr
> avl_dacfifo: Add support for partial avalon transfers
> avl_dacfifo: Grey coder/decoder integration
> common: Add grey coder and decoder modules
> avl_dacfifo: Add avl_dacfifo_byteenable_coder
> avl_dacfifo: Few cosmetic changes on avl_dacfifo_wr
> avl_dacfifo: Add support for MEM_RATIO 32
> avl_dacfifo: Integrate util_delay into dac_xfer_out path
> avl_dacfifo: dma_ready was muxed incorrectly
> avl_dacfifo: Fix the avalon address switch
> avl_dacfifo: Fix a few control signals
> avl_dacfifo: Fix the avl_write generation
> avl_dacfifo: Fix alv_mem_readen generation
> avl_dacfifo: Few cosmetic changes on avl_dacfifo_wr
> util_delay: Initial commit
> avl_dacfifo: Fix indentation for acl_dacfifo.v
> avl_dacfifo: Add a parameter AVL_ADDRESS_WIDTH
> altera/ad_mem_asym: Fix grounded bus for marco instance
> adi_ip.tcl: Use analog.com for interface vendor
> interfaces: Add dependencies to rule
> interfaces: Simplify Makefile
> m2k: Add scale correction option. Update parameters
> axi_ad9963: Add scale only correction option
> ad_iqcor: Add scale only correction option
> pzsdr2/ccfmc: enable eth1 mdio
> usdrx1- spi/mlo fixes
> motcon2_fmc: Explicitly assign ETH0 MDIO to EMIO
> axi_hdmi_rx- move data to an iob
> fmcadc2/vc707- spi clock reg can't be on iob
> daq3/kcu105- reorder refclk constraints
> kcu105- vivado now depends on order of constraints?
> kcu105- remove ethernet delay ctrl false path
> library: Sort Makefile
> m2k: Refresh Makefile
> util_adxcvr- 2016.4 gthe4 updates
> zcu102- 2016.4 updates
> adrv9371x fix dacfifo name
> quartus optimization for frequency
> alt_mul- qsys replacement
> alt-jesd- constraints update
> a10soc- 16.1- hsp sdram reset
> a10soc- fix version check
> resolving conflicts
> alt-mem-asym - replace mega function cores
> adi-ip-alt allow changing device family
> alt_mem_asym- qsys component
> license: Fix VHDL license header
> scripts: Update required tool versions
> Fix VHDL files license header, second try
> Fix VHDL files license header
> axi_usb_fx3: Add missing ports
> all: Update license for all hdl source files
> util_fir_int: Force 1/8 filter input data rate
> axi_adc_decimate/cic_decim: Fix clk_enable warning
> util_tdd_sync: add missing ports
> Remove duplicare wire declaration
> Add missing ad_serdes_out interface ports
> daq2/a10gx- constraints remove 16.0
> axi_ad9963: Update constraints as adc_common and dac_common paths have been renamed
> up_dac_common: rename internal signals
> a10gx- change ddr to 1G
> altera- add version check
> altera- infer latest versions
> altera- default to latest version
> version check- change to critical warning
> axi adc cores: Add missing ports to up_adc_common instance
> axi dac cores: Add missing ports to up_dac_common instance
> fmcadc5-sync: added a convenience timer
> axi_ad5766: Add missing ports to up_dac_common instance
> axi_ad5766: sdo_mem size is 3
> axi_ad5766: Delete redundant parameters
> axi_generic_adc: Update port names for up_adc_common instance
> fmcadc5- syntax/port name fixes
> up_adc_common- port name changes
> hdlmake.pl updates
> axi_fmcadc5- remove pack-driver is too late
> axi_fmcadc5- sign-extend and interleave (core is too late)
> ad9625- add an option to control cs monitoring
> library/up_adc_common- add sref sync option
> library/axi_fmcadc5_sync- remove dependecy on adc-core (driver shows up late)
> axi_ad9739a: Fix DDS set frequency
> axi_ad9371: Update dac_clk_ratio to 2
> axi_fmcadc5_sync- raw inputs & constraint fixes
> axi_fmcadc5_sync- raw inputs & constraint fixes
> hdlmake.pl updates
> axi_fmcadc5_sync- calcor added
> axi_ad9434: Fix input data rate
> ad77681evb: Initial commit
> spi_engine_offload: Add a CDC module for trigger reception
> spi_engine: Define parameter inside the module statement
> adrv9371x/a10soc: Fix constraints
> zcu102: Automatic IP version update fix
> zcu102: Automatic IP version update
> usrpe31x: Automatic IP version update
> pzsdr*: Automatic IP version update
> change pl ddr clock to 1G
> axi_fmcadc5_sync: add a calibration signal generation
> daq2: zc706: Increase DAC FIFO size
> adaq7980: Update tcl command for IP configuration
> ad5766_sdz: Update tcl commands for IP configuration
> hdlmake- updates
> fmcadc5- remove stand alone psync
> fmcadc5- remove psync module
> adi_boadr- disconnect and remove unused ports
> fmcadc5- sync updates
> fmcadc5-sync- add ldo psync
> util_adxcvr: Fix parameter setup at instantiation
> axi_ad5766: Fix parameter name for up_dac_common
> ad5766_sdz/zed: Fix i_iobuf_reset width
> spi_engine_interconnect: Delete dependency defined for S1_CTRL interface
> util_pulse_gen: Add Makefile
> adaq7980/zed: Update Makefile
> spi_engine: Expose DATA_WIDTH to software
> util_pulse_gen: The valid period is stored in pulse_period_d
> adaq7980: Add an trigger generator for SPI offload
> adaq7980_sdz: Initial commit
> spi_engine_execution: Define port dependencies for SDI ports
> axi_spi_engine: Define ports dependencies for up_* interface
> ad5766_sdz: Fix the PIN assignment
> cn0363: Update block design
> up_dac_common: Increase datawidth of dac_datarate
> ad5766_sdz: Fix DMA data path
> axi_ad5766: Add Makefiles for the core
> axi_ad5766: Preserve consistent coding style
> ad5766_zed: Add an IOBUF to the reset line
> ad5766: Integrate the new axi_ad5766 into the project
> util_pulse_gen: Add configuration interface for 'pulse period'.
> interface: Update spi_engine_offload_ctrl definition
> spi_engine: Fix CMD_FIFO_VALID generation
> axi_ad5766: Initial commit
> ad5766_sdz : Fix SPI interface connection
> spi_engine: Add dependency for unused interfaces
> ad5766_sdz: Initial commit
> ad9162- add iq swap
> axi_ad9361: Fix ad_cmos_out instantiations
Signed-off-by: Michael Hennerich <[email protected]>
