M2k: prepare for alpha - v0.16
Submodule linux 05dd68f..085bcdf:
> iio: m2k-trigger-ad: Add streaming attribute
> iio: m2k-trigger-ad: Add triggered attribute
> iio: m2k-logic-analyzer: Add streaming attribute
> iio: m2k-logic-analyzer: Add triggered attribute
> iio: m2k-adc: Add calibration scale support
> iio: m2k-dac: Add calibration scale support
Submodule buildroot 628b56c..0a4e137:
> board/pluto/S23udc: Add fw_version context attribute
> board/pluto/S23udc: strip leading "adi," from model contect attribute
> board/pluto/S23udc: Add ad9361-phy,model context attribute
Submodule u-boot-xlnx 4bdff59..9bc27b7:
> rsa: Fix build with OpenSSL 1.1.x
Submodule hdl c1e990b..2b8adca:
> adrv9361- inverted clock
> axi_ad9361- allow clock inversion based on hardware
> cftl: Delete unused projects and libraries
> library- vivado 2017.2 update
> daq1_zed: Lower the adc and daq clock to 450MHz
> interface: Update the transceiver interfaces
> common/microzed: Enable PS CLK1 = 200MHz
> common/a10soc: Update configuration for emif plddr4 IP
> altera/ad_mem_asym: Delete it, QSYS flow is used
> [axi|avl]_dacfifo: Create a separate bypass module for altera/xilinx
> common/a10gx: Chance SPI frequency from 128KHz to 10 MHz
> axi_adcfifo: Add missing constraints
> adrv9379: Change the DMA clock to 250
> arradio/c5soc- rd10102013_979 fix
> adrv9371: a10soc: Whitespace cleanup
> arradio- add control/status ports
> arradio- add control/status ports
> adrv9379: Initial commit
> axi_ad9379: Initial commit
> dm2k: Drive the ADC DMA valid from the trigger extracting core
> axi_logic_analyzer: Compensate the 4 word latency of util_var_fifo
> util_extract: Compensate 4 word latency
> util_var_fifo: Set fix latency of 4 for all interpolation values
> jesd204_rx: rx_ctrl: Fix typo
> axi_ad9963: Moved RX configuration bit SCALECORRECTION_ONLY to bit 9
> adrv9364/ccbox- input rf protection
> adrv9361/ccbox- sort gpio - accidental multiple drivers
> library- add a timer for quick start
> adrv9361-ccbox/ccfmc- adl5904/gpio updates
> adrv9361- add adl5904
> adrv9371x: altera: Convert to ADI JESD204
> altera: adi_jesd204: Export link domain reset
> altera: adi_jesd204: Disable FPLL phase alignment mode
> altera: adi_jesd204: Enable avmm_busy flag in the link FPLL register map
> jesd204: jesd204_rx: Don't expose internal states on the status interface
> axi_dmac: Better support debug IDs when ID_WIDTH != 3
> adrv9371x_zcu102: Initial commit
> adrv9371x_kcu105: Initial commit
> adrv9371x/common: Remove ila_adc and ila_os_adc
> adrv9371x/common: Fix axi_ad9371_dacfifo/dac_rst assignamen
> adrv9371x: Separate ps7 assignaments from common
> common/zcu102: Fix ps8 ref clock 0 frequency assignament
> common/zcu102: Add gpio_t connections
> avl_dacfifo: Update IP to qsys flow
> adrv9371x: DAC_FIFO should get the dma_rst from sys_dma_rstgen
> axi_dacfifo: Update constraints
> fmcomms11: Connect data underflow to the core
> axi_dacfifo: Major update and redesign
> altera: jesd204_phy: Fix indention issues
> daq2: Add support for Arria10 SoC platform
> daq2: daq2_qsys.tcl: Convert to ADI JESD204
> daq2: daq2_qsys.tcl: Rework peripheral addresses
> library: Add ADI JESD204 wrapper for Altera/Intel platforms
> library: Add JESD204 PHY wrapper for Arria10 Native PHY
> jesd204: Add soft logic PCS
> jesd204: Add Altera/Intel IP support
> jesd204: jesd204_tx: Add dummy valid for the TX data interface
> jesd204: ilas_mem: Rework to be more Altera friendly
> util_cdc: Add helper function for creating constraints for the CDC blocks
> adi_ip_alt.tcl: ad_ip_parameter: Allow to specify additional properties
> adi_ip_alt.tcl: Allow to add TCL files to the fileset
> jesd204: axi_jesd204_{rx,tx}: Add external link domain reset
> util_adcfifo: Remove always false check
> util_adcfifo: Fix data corruption at faster DMA clock rates
> microzed: Add a secondary 200 MHz clock for PS7
> axi_logic_anlayzer: Fix trigger AND logic
> axi_streaming_dma_tx_fifo: Fix drain logic
> axi_i2s_adi: Make constraints work on UltraScale
> jesd204: axi_jesd204_rx_regmap_tb: Add missing dependency
> axi_dmac: axi_dmac_hw.tcl: Set associated reset and addressable point for the interrupt interface
> alt_mem_asym: Set read latency to 1 clock cycle
> rfifo- drive valid outs
> hdlmake.pl - updates
> fmcomms2/zc702- pmod1 udc, pmod2 gpio
> fmcomms5/zc702- pmods as gpios
> adv7511/zc702- pmods as gpios
> projects/zc702- free pmod gpio for customization
> adrv936x- readme updates
> adrv936x- readme updates
> adrv936x- readme updates
> Update README.md
> util_adxcvr- defaults for es
> hdlmake.pl- updates
> jesd204: Use consistent naming scheme for CDC blocks
> jesd204_tx: Use the CDC sync_bits helper to synchronize the SYNC~ signal
> axi_jesd204_tx: Remove IRQ events for now
> axi_jesd204_tx: jesd204_up_tx: Use two dimensional array for up_cfg_ilas_data
> jesd204_tx: Remove duplicated file
> jesd204: rx_tb: Fix some incorrect signal connections
> axi_adxcvr: Avoid implicit signal truncation warning
> common: a10soc: Use correct DDR memory reference clock type
> ad9361- clkdiv to util_ad9361_divclk
> fmcomms5- bd- data flow format
> fmcadc2: Fix connection between a db port and a net
> axi_ad9671: Fix typo
> axi_ad9625: Fix typo
> util_cdc: Update to verilog-2001 coding standard
> util_axis_resize: Coding style updates
> adrv936x- bd.tcl in data flow format
> axi_ad9361: Update constraint file
> ad738x_fmc: Supported sample rate is 3MSPS
> ad738x_fmc: Configuration update/fix
> spi_engine: Add support for max 4 SDI lines
> ad738x_fmc: Initial commit
> m2k: Move ADC hardware gain correction from the AD9963 IP to AXI_ADC_DECIMATE IP
> axi_adc_decimate: Add correction at the end of the decimation chain
> fmcomms2_bd- keep data flow format
> common: a10soc: Mark external reset as asynchronous
> avl_adxcvr: Perform octet order swap
> avl_adxcvr: Simplify TX lane mapping
> m2k: Enable correction for the interpolation module
> axi_dac_interpolate: Add correction at the begining of the interpolation chain
> axi_ad9361: Update the PPS receiver module
> util_axis_fifo: Fix some data width mismatches
> util_axis_fifo: Switch to Verilog-2001 style parameter declaration
> axi_dmac: Set axi4lite address space size to 4k
> axi_dmac: src_axi_stream: Terminate data mover m_axi_last signal
> axi_dmac: axi_dmac_hw.tcl: Disable unused interfaces instead of not creating them
> axi_dmac: dest_axi_mm: Use fixed wstrb signal
> axi_dmac: Comment out unused src_response interface
> axi_dmac: Fix some data width mismatches
> library: Match s_axi_{awaddr,araddr} signal width to peripheral memory map size
> util_upack: util_upack_hw.tcl: Disable unused interfaces instead of not creating them
> util_cpack: util_cpack_hw.tcl: Disable unused interfaces instead of not creating them
> axi_ad9144: axi_ad9144_hw.tcl: Disable unused interfaces instead of not creating them
> axi_ad9144: Avoid implicit signal truncation warning
> util_adcfifo: Avoid implicit signal truncation warning
> axi_ad9680: axi_ad9680_hw.tcl: Fix typo
> axi_adxcvr: Avoid warning about unknown synthesis attribute
> adi_project_alt.tcl: Disable a few warnings generated by standard components
Signed-off-by: Michael Hennerich <[email protected]>
