M2k: prepare for alpha - v0.17
Submodule linux dbfd83f..8e78391:
> drivers/mtd/spi-nor/spi-nor: Fix malicious locking support for n25qxxx
> dts: zynq-m2k.dtsi: QSPI MTD add compatible n25q512a
> m2k-fabric: Allow to update input and output configuration independenlty
> iio: m2k-fabric: Remove unnecessary distinction between Rev C and non Rev C
> iio: m2k-fabric: Remove Rev. B support
> iio: m2k-fabric: Use same extended name for both NEG/POS supplies
> dts: zynq-m2k-revc: Correct inverted pos and neg supply powerdown gpios
Submodule buildroot 0a4e137..6ae9f88:
> package: libiio: Bump to version 0.12
> package/libiio/libiio.mk: Push to version 0.11
Submodule u-boot-xlnx 9bc27b7..efdb9e8:
> configs: zynq-common: Redo SF lock upon button press and failed boot
Submodule hdl 2b8adca...3e3955c:
> avl_dacfifo: Fix avl_address generation
> avl_dacfifo: Control the avl_burstcount inside the FSM
> avl_dacfifo: Fix the last address buffer control
> avl_dacfifo: dma_last_beats is transfered to avalon clock domain, without conditioning
> daq2: Data underflow of DAC FIFO is monitored by the device core
> avl_dacfifo: End of burst is not always end of a transaction
> axi_streaming_dma_rx_fifo: fix period_count clock and TLAST
> fmcadc5: Allow JESD reset from the ADC core, useful for synchronization
> fmcadc5: Disable constraints for jesd sysref in order to remove critical warning
> axi_dmac: Align the data_ready to data
> daq2_zcu102: Fix typo
> Require Vivado 2017.2.1 for all zcu102 projects
> adrv9371x_zcu102: Fix rx_div_clk constraint placement
> fmcadc5: Update make
> fmcadc5: Update to the ADI JESD interface
> Make: Update makefiles
> library: Update
> daq2, daq3: zcu102: Update constraints
> daq2: Set correct transceiver type for UltraScale projects
> adrv9371x: Set correct transceiver type for UltraScale projects
> axi_adxcvr: Correctly report the transceiver type in the register map
> adrv9371x: zcu102: Fix lane mapping
> adrv9371x: zcu102: Fix QPLL feedback divider
> fmcjesdadc1: Update A10GX/A10SOC projects to the ADI JESD framework
> zcu102 constraints description/cosmetic updates
> zcu102: Update to rev 1.0
> fmcomms2: Connect dac data underflow
> axi_dmac: Reset fifo_rd_data without delaying the valid data
> avl_dacfifo: Fix dac_xfer_req generation
> avl_dacfifo: Fix reset architecture in avl_dacfifo_rd
> avl_dacfifo: Fix the loopback of avl_xfer_req
> avl_dacfifo: Fix write enable generation
> avl_dacfifo: Fix reset of write address register
> daq3: Disable start synchronization for the ADC DMA
> daq2: Disable start synchronization for the ADC DMA
> avl_dacfifo: Refactor the fifo
> daq2/zcu102: Pin Swap for ZCU102 Rev1.0
> daq3: A10GX, overconstrained failing paths
> daq3: A10GX, updated to the ADI JESD204
> jesd204: Added additional input registers to jesd204_soft_pcs_rx, when lane rate is over 10Gbps
> daq2: A10GX, added additional interconnect pipelining
> adi_env: Normalize environment variables
> adrv9371x: A10GX, added extra pipelining in the interconnect in order to improve timing
> daq2: A10GX, added extra pipelining in the interconnect in order to improve timing
> daq2: A10GX, connect dac_fifo_bypass to gpio
> daq2: A10SOC, added dac fifo
> daq2: A10GX, added dac fifo
> axi_ad9361: Fix dac_datarate counter implementation
> axi_dmac: Reset fifo_rd_data when DMA is off - v2
> usdrx1/a10gx: Add external flash support
> fmcjesdadc1/a10gx: Add external flash support
> daq3/a10gx: Add external falsh support
> adrv9371x/a10gx: Add external flash support
> util_dacfifo: Integrate grey coder/decoder module
> axi_dmac: Reset the fifo_rd_data if the DMA is off
> a10gx: Force all used tiles to high speed, in order to improve timing
> daq1_zed: Lower the adc and daq clock to 450MHz
> arradio: Changed ADC DMA buswidth connection to the DDR to 128 bits
> daq2/a10gx: Add cfi_flash to qsys
> adrv9371x/a10soc: For receive paths SYNC_TRANSFER must be enabled
> axi_ad9361: Fix incorrect merge
> axi_dmac: Control s_axis_user/fifo_wr_sync validity
> arradio: Fix the last incorrect merge
> axi_dmac: Fix the last incorrect merge
> axi_ad9361: Fix the last incorrect merge
< adrv9361- inverted clock
< axi_ad9361- allow clock inversion based on hardware
< cftl: Delete unused projects and libraries
< library- vivado 2017.2 update
< daq1_zed: Lower the adc and daq clock to 450MHz
> Merge branch 'dev' into hdl_2017_r1
> A10GX: Update DDR3 configuration
> license: Update old license headers
> arradio: Changed ADC DMA buswidth connection to the DDR to 128 bits
> axi_ad9361: Fix altera lvds interface, reverting to an older working version
> arradio: Changed clock domain of the ADC and DAC path to half the interface clock
> util_clkdiv: Added altera version
> ad9361/xilinx- missing up_rstn
> ZCU102: SPI assign chip selects individually
> hdl/library- fix syntax errors/synthesis warnings
> common: a10soc: Avoid unnecessary DMA clock domain crossing bridge insertion
> up_clock_mon: Explicitly truncate d_count during up_d_count assignment
> jesd204: jesd204_up_common: Rename clock monitor instance to i_clock_mon
> jesd204: jesd204_up_ilas_mem: Fix blocking assignment
> axi_dmac: axi_dmac_hw.tcl: Set read and write issuing capabilities
> axi_dmac: axi_dmac_hw.tcl: Set default DMA_LENGTH_WIDTH to 24
Signed-off-by: Michael Hennerich <[email protected]>
