alpha - v0.13

M2k: prepare for alpha - v0.13

Submodule linux 3fb3442...751f62f:
  > clk: axi-clkgen: Add support for fractional dividers
  > zynq_m2k_defconfig: Disable axi-clkgen driver
  > zynq-m2k.dtsi: Disable frequency scaling for now
  > zynq-m2k.dtsi: Don't force FCLKs to be enabled
  > iio: m2k-logic-analyzer: Add power-down attribute
  > iio: ad9963: Generate TX interface clock
  > clk: adf4360: Disable clock on remove
  > iio: ad_adc: Allow accessing registers of the slave core
  > iio: ad9963: Disable auxillary DAC
  > iio: m2k-logic-analyzer: Implement direct register access
  > iio: xadc: Power-down ADC when driver is removed
  > zynq-m2k: Set CPU frequency operating points
  < Revert "zynq-m2k-reva.dts/zynq-zed-adv7511-m2k-revc.dts: Remove logic analyzer MMCM"

Submodule hdl 454e6c0..7cff121:
  > hdlmake: Fix util_clkdiv Makefile issue. sort library master Makefile
  > hdlmake updates
  > fmcadc5- hdl sync handling
  > adi_board- keep port delete simple
  > axi_fmcadc5_sync- updates
  > axi_fmcadc5_sync- updates
  > fmcadc5-sync- try sync in hdl
  > cn0363: Reorder the configuration settings of the fir filters
  > altera/ad_cmos_in: Define supported DEVICE_TYPE options
  > altera/ad_cmos_in|out: Delete redundant parameter
  > avl_dacfifo: Update constarint file
  > avl_dacfifo: Fix read/write address switching
  > xilinx/ad_cmos_in|out: Delete redundant parameter
  > m2k:standalone, remove power optimizations as they are performed manually
  > daq2: Fix typo
  > cn0363: Fix typos and mistakes made in 0737183
  > daq2/zcu102: Update tcl command for IP configuration
  > daq2/kcu105: Update tcl command for IP configuration
  > daq1: Fix typo
  > adv7511/kcu105: Update tcl command for IP configuration
  > axi_dacfifo: Fix Makefile
  > avl_dacfifo: Update constraints
  > avl_dacfifo: Use the ad_mem_asym for altera
  > avl_dacfifo: Delete redundant file
  > adv7511: audio_clkgen: Disable clock source buffer insertion
  > adv7511: audio_clkgen: Disable phase alignment
  > adv7511: audio_clkgen: Infer input clock frequency
  > adv7511: audio_clkgen: Disable unused pins
  > fmcomms7: Update IP instantiations
  > fmcomms11: Update IP instantiations
  > fmcomms5: Update UP instantiations
  > fmcomms2: Update IP instantiations
  > fmcjesdadc1: Update IP instantiations
  > daq3: Update IP instantiations
  > daq1: Update IP instantiations
  > cn0363: Update IP instantiations
  > kc705_common/adv7511: Update IP instantiations
  > pzsdr1/pzsdr2: audio_clkgen: Disable clock source buffer insertion
  > pzsdr1/pzsdr2: audio_clkgen: Disable phase alignment
  > pzsdr1/pzsdr2: audio_clkgen: Infer input clock frequency
  > adrv9371/a10soc: Integrate the avl_dacfifo into project
  > avl_dacfifo: Initial commit
  > axi_dacfifo: Move the axi_dac_fifo_bypass module to util_dac_fifo_bypass
  > ac701_common/adv7511: Update IP instantiations
  > axi_hdmi_tx: Fix assignment type
  > m2k: zed: Fix default HDMI clock frequency
  > axi_clkgen: Propagate clock settings to output pins
  > axi_clkgen: Infer CLKIN period
  > axi_clkgen: Add interface definitions for clock inputs/outputs
  > axi_clkgen: Add enable parameters for secondary clock inputs/outputs
  > axi_clkgen: Add type hints for parameters
  > axi_clkgen: Remove unused parameters for third clock output
  > common: zed/zc702/zc706/mitx045: audio_clkgen: Disable phase alignment
  > common: zed/zc702/zc706/mitx045: Set audio clkgen clock source type
  > common: zc702/zc706/mitx045: audio_clkgen: Infer input clock frequency
  > axi_ad9434: ad_serdes_clk instantiation should reflect all important configurations
  > ad_serdes_in: Fix generate block
  > ad_serdes_clk: Fix generate block
  > ad_mmcm_drp: Fix generate block
  > ad9434_fmc: Port redeclaration as a wire is not allowed
  > axi_ad9434: Port redeclaration as a wire is not allowed
  > axi_ad9250: Port redeclaration as a wire is not allowed
  > axi_ad9625: Port redeclaration as a wire is not allowed
  > m2k: zed: Run video DMA at higher clock rate
  > common: zed: audio_clkgen: Infer input clock frequency
  > axi_dmac: post_propagate(): Handle mappings with multiple address segments
  > axi_dmac: post_propagate(): Handle address segments with offsets
  > fmcomms2/zc702: Fix Warning[Synth 8-2611]
  > axi_ad9361: Fix Warning[Synth 8-2611]
  > ad_tdd_control: Optimize the burst_counter logic
  > fmcadc5/vc707, lpm mode
  > pzsdr1/pzsdr2- ccbox added tws
  > m2k: zed, cleaned up some warnings
  > m2k: ip automatic version update
  > library: axi_i2s_adi, axi_spdif_rx, axi_spdif_tx, util_axis_fifo rename ports to lowercase
  > axi_dmac: Remove reset from up_rdata and gate when unused
  > axi_dmac: Add missing reset for cyclic and xlast flags
  > axi_adc_trigger: Reduce AXI address width
  > axi_adc_decimate: Reduce AXI address width
  > axi_dac_interpolate: Reduce AXI address width
  > axi_logic_analyzer: Reduce AXI address width
  > axi_dmac: Reduce AXI address width
  > up_axi: Allow to configure AXI address width
  > scripts/adi_ip.pl: Infer register map range from address width
  > axi_logic_analyzer: Add missing reset wire declaration
  > m2k: Move the BRAM generation outside of the variable fifo IP
  > util_var_fifo: Assign data_out and data_out_valid based on fifo_active
  > util_var_fifo: Disable BRAMs if the depth of the FIFO is 0.
  > util_var_fifo: Move BRAM outside of the core so that it can be generated using Xilinx IP
  > axi_ad9963: Integrated ADC/DAC clock enables
  > up_dac_common: Added clock enable control for the DAC cores
  > up_adc_common: Added clock enable control for the ADC cores
  > axi_dmac: Configure AXI address width according to the mapped address space
  > axi_ad9963: Disable delay_clk port when IODELAYs are unused
  > scripts/adi_ip.tcl: adi_set_ports_dependency(): Allow to specify tie-off value
  > m2k: standalone: Rework PS7 clocking
  > m2k: standalone: Disable 200MHz clock
  > m2k: standalone: Disable 2nd PS7 reset port
  > m2k: Standalone, enabled power optimization
  > scripts: Created ADI_POWER_OPTIMIZATION parameter for enabling power optimizations in the implementation stage
  > axi_dac_interpolate: Register output mux signal
  > axi_dac_interpolate: Reduce filter_mask signal width
  > axi_dac_interpolate: Move processing pipeline to own sub-module
  > axi_adc_decimate: Do proper sign extension in bypass mode
  > axi_adc_decimate: Gate unused filter parts
  > util_cic: Allow partial gating of CIC comb and int stages
  > axi_adc_decimate: Re-implemented FIR filter
  > axi_adc_decimate: Use sequential processing for CIC comb stage
  > axi_adc_decimate: Register output mux control signal
  > axi_adc_decimate: Re-implement CIC filter
  > Add CIC filter helper module
  > axi_adc_decimate: Reduce filter_mask register size
  > axi_adc_decimate: Move processing pipeline to own sub-module
  > axi_logic_analyzer: Allow changing data pins direction to output only after data is available from the DMA or if the output is set from a register for that specific pin
  > m2k: Connect logic_analyzer path to clk_out instead of clk
  > axi_logic_analyzer: Allow only data[0] to be used as alternative clock.
  > axi_ad9963: Changed TX path from serdes to ddr.
  > m2k: standalone: Disable DMA debug registers
  > axi_dmac: Make debug register optional
  > m2k: standalone: Set static switching activity for the reset signals
  > m2k: Disable AD9963 core RX datapath again
  > axi_ad9963: Sign extend ADC data when processing is bypassed
  > util_axis_fifo: Improve clock gating of registers and BRAM
  > axi_ad9963: Allow to disable the IDELAYs on the ADC data path
  > ad_lvds_in: Allow to disable IDELAY
  > ad_lvds_in: Use "SAME_EDGE" mode
  > m2k: Rework clocking domains
  > m2k: Replace logic analyzer MMCM
  > m2k: Remove channel pack core for now
  > axi_adc_trigger: Temporarily disable trigger reporting in register map
  > m2k: Connected adc/dac resets to decimation/interpolation cores
  > axi_dac_interpolate: Make dac_reset external
  > axi_adc_decimate: Make adc_reset external
  > m2k: Renamed l_clk to adc_clk and rst to adc_rst
  > axi_ad9963: Separated adc/dac clock and reset
  > m2k: Updated project to use new tx path with serdes
  > axi_ad9963: updated tx path
  > ad_serdes_out: allow selection between DDR/SDR configuration and output single ended data
  > ad_serdes_clk: allow for single ended clock input, made BUFR_DIVIDE configurable
  > m2k: Reduce AXI interconnect utilization
  > Add a helper module to combine a AXI read-only and a AXI write-only interface into a read-write interface
  > axi_ad9963: Remove extra pipeline stages on register read path
  > axi_ad9963: Disable unused features of the register map
  > up_dac_common: Allow to disable GPIO registers
  > up_adc_common: Allow to disable GPIO and START_CODE registers
  > kcu105: ip automatic version update
  > Makefiles: Change MMU enabling parameter for altera designs from MMU to NIOS2_MMU
  > pluto: cleaned up some warnings
  > motcon2_fmc: cleaned up some warnings
  > cftl_std: cleaned up some warnings
  > cftl_cip: cleaned up some warnings
  > mitx045: ip automatic version update
  > microzed: ip automatic version update
  > usdrx1: ip automatic version update
  > motcon2: ip automatic version update
  > usb_fx3: ip automatic version update
  > pluto: ip automatic version update
  > imageon: ip automatic version update
  > cftl_cip: ip automatic version update
  > cftl_std: ip automatic version update
  > all: Update verilog files to verilog-2001
  > Ip automatic version update: fmcadc2, fmcadc5
  > Ip automatic version update: common/board
  > spi_engine: Fix CMD_FIFO_VALID generation
  > adi_project- try something simple first
  > adi_board- create_bd_cell replacement
  > Ip automatic version: Update ad*/common/ad*_bd.tcl

Submodule buildroot 4ec88d2..50c07c5:
  > board/pluto/S40network: Be less verbose - redirect to syslog
  > board/pluto/update.sh: make_diagnostic_report() include uboot env
  > board/pluto/update.sh: handle_boot_frm() only match mtd0 and mtd1
  > board/m2k/S16xadc: Unbind XADC driver during init
  > libiio: Set git hash manually since it can't be computed

  dirty - libiio build from 263bd0802cb405f1025b83dbce468481b6516cd3

Submodule u-boot-xlnx 26e73f4..4bdff59:
  > include/configs/zynq-common: Be less verbose
  > board/xilinx/zynq/board: default env if button pressed
  > configs/zynq_pluto_defconfig: BOOTDELAY = 0
  > cmd/version.c: XADC power down after use
  > cmd/xadcps.h: Fix PD0 and PD1 assignments

Signed-off-by: Michael Hennerich <[email protected]>

alpha - v0.12

m2k-fw: Prepare for v0.12

Submodule linux 3232973..3fb3442:
  > Revert "zynq-m2k-reva.dts/zynq-zed-adv7511-m2k-revc.dts: Remove logic analyzer MMCM"
  > m2k-dac: Fix dma_sync permissions
  > Remove zynq-zc706-adv7511-m2k.dts
  > zynq-m2k-reva.dts/zynq-zed-adv7511-m2k-revc.dts: Remove logic analyzer MMCM
  > zynq-m2k.dtsi: Mark PL330 DMA as disabled.
  > zynq_m2k_defconfig: Disable drivers that are not needed
  > zynq_m2k_defconfig: Enable CPU frequency scaling
  > zynq_xcomm_adv7511_defconfig: Enable AD9963 support
  > zynq_xcomm_adv7511_defconfig: Enable M2K_DAC support

Submodule buildroot 2681fa7..4ec88d2:
  > package/libiio/libiio.mk: until there is a new release use current HEAD
  > package/libiio/libiio: Build libiio from the faster branch 82a9cc0
  > Merge branch 'pluto' of https://github.com/analogdevicesinc/buildroot into pluto
  > board/pluto: cleanup init scripts

Submodule u-boot-xlnx 413748e..26e73f4:
  > include/configs/zynq-common: Add variable to support all versions of Pluto
  > zynq-common: Fix device tree patching for multi dt FIT images

Submodule hdl 09bcecb..454e6c0:
  > daq2- ad-ip-instance & ad-ip-parameter
  > xilinx- ad-ip-instance & ad-ip-parameter
  > zc706- ad-ip-instance & ad-ip-parameter
  > adi_board- add auto ip version handling
  > library: Delete all adi_ip_constraint process call
  > util_clkdiv: constraints should be applied LATE for this core
  > constraints: constraint files should be specified at adi_ip_files
  > adi_ip- remove adi_ip_constraints
  > adi_ip- a little rearrangement
  > axi_ad9122: Update constraint files
  > Makefile: Update Makefiles for libraries
  > axi_dmac: Propagate awlen/arlen width through the core
  > ad_axi_ip_constr.xdc: Delete file
  > library: Update scripts with new constraints
  > fmcomms2: Update constraints file paths
  > restructure: Move xilinx specific constraints to /library/xilinx/common/
  > ad9963: Remove localparams from module parameter list
  > m2k: standalone: Assign 0 to unused GPIO inputs
  > adrv9371x/altera- xilinx/chip-select consistency
  > adi_ip: Set up SCOPE_TO_REF for xdc and save the core
  > fmcomms2: Use the new constriants from 335fef0
  > ad_axi_ip_constr: Split up this constraint file into separate files
  > m2k: Remove redundant s_axi_{aclk,aresetn} assignment
  > adrv9371x/altera- gpio equivalency fix
  > adrv9371x/a10gx- gpio matching
  > ad9684- fix sdc typo
  > daq1/a10gx- fix project to compile
  > adrv9371x/a10soc- altera reset synchronizer false path?
  > fmcjesdadc1: Update xcvr configuration to the default one used for this board
  > a5soc- add ddr3 location assignments
  > altera/a10gx- daq1/fmcomms2 fix typos
  > altera srf files do not work
  > a5gte- add constraints for tq
  > a10gx- ignore preliminary timing model warnings
  > arradio/c5soc- reset false path for vga dma
  > make updates
  > arradio/c5soc- remove qsys files
  > arradio/c5soc- qsys-script flow
  > altera- ignore preliminary timing messages
  > arradio/c5soc- updated to new framework/16.0
  > arradio/c5soc- critical warnings fix
  > arradio/c5soc- critical warnings fix
  > ad9361- delay initialization

Signed-off-by: Michael Hennerich <[email protected]>

alpha - v0.11

submodule update

Signed-off-by: Michael Hennerich <[email protected]>

alpha - v0.1

alpha v0.1