[tlul, shim] Externalize Caliptra registers #12
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andrea-caforio
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hw/ip/tlul/rtl/tlul_adapter_shim.sv
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| parameter bit [31:0] SHIM_NAME_1 = 32'hCAFEBABE, | ||
| parameter bit [31:0] SHIM_VERSION_0 = 32'h00000001, | ||
| parameter bit [31:0] SHIM_VERSION_1 = 32'h00000000, | ||
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| parameter bit [11:0] SHIM_REGISTER_ADDRESS_OFFSET = 12'h100, |
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Should this be renamed to DV_REGISTER_ADDRESS_OFFSET?
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And, I think this would need to be of width ADDR_WIDTH actually.
hw/ip/tlul/rtl/tlul_adapter_shim.sv
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| // DV device interface (DV to TLUL). | ||
| input logic tlul_dv_i, | ||
| output logic tlul_hld_o, | ||
| input logic [ADDR_WIDTH-1:0] tlul_addr_i, | ||
| input logic tlul_write_i, | ||
| input logic [DATA_WIDTH-1:0] tlul_wdata_i, | ||
| input logic [MASK_WIDTH-1:0] tlul_wstrb_i, | ||
| input logic [2:0] tlul_size_i, | ||
| output logic [DATA_WIDTH-1:0] tlul_rdata_o, | ||
| output logic tlul_error_o, | ||
| input logic tlul_last_i, | ||
| input logic [USER_WIDTH-1:0] tlul_user_i, | ||
| input logic [ID_WIDTH-1:0] tlul_id_i, | ||
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The tlul_ prefix here is a bit confusing. Because what's coming in here can both go to TLUL or the port below. One could say that this is the primary interface of the shim, whereas the newly added interface is the secondary interface.
hw/ip/tlul/rtl/tlul_adapter_shim.sv
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| input logic [USER_WIDTH-1:0] tlul_user_i, | ||
| input logic [ID_WIDTH-1:0] tlul_id_i, | ||
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| // DV host interface (DV to internal registers). |
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Maybe clarify the comment by saying that accesses for which the internal_access signal gets set are routed to this interface?
hw/ip/tlul/rtl/tlul_adapter_shim.sv
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| // file and those targeting OpenTitan registers, with the latter ones being translated into TLUL | ||
| // requests while the other requests are relayed to the internal register file. | ||
| logic internal_access; | ||
| assign internal_access = |(tlul_addr_i[11:0] & SHIM_REGISTER_ADDRESS_OFFSET); |
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Here we should probably compare the full address now that the shim becomes much more generic (by outputting the unmapped requests again) - I think this shim may get used pretty widely in the future.
hw/ip/tlul/rtl/tlul_adapter_shim.sv
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| input logic [ID_WIDTH-1:0] tlul_id_i, | ||
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| // DV host interface (DV to internal registers). | ||
| output logic dv_dv_o, |
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I don't have a good idea regarding how to distinguish these signals of the secondary port from the primary above. I think some form of prefix is needed. Given that we call these registers "internal" we could maybe use int_?
andrea-caforio
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@vogelpi Thank you for the review. Let's see whether the custom bus protocol has a name. :-) |
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Move Valid-Hold-internal registers to a separate module with its own VH interface and redirect requests to it. Signed-off-by: Andrea Caforio <[email protected]>
andrea-caforio
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CHANGE AUTHORIZED: hw/ip/tlul/rtl/tlul_adapter_shim.sv This PR touches the TLUL - VH adapter which is expected and fine. |
Move Caliptra-internal registers to a separate module with its own DV interface and redirect shim requests to it.