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[tlul, shim] Externalize DV registers
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Move DV-internal registers to a separate module with its own DV
interface and redirect shim requests to it.

Signed-off-by: Andrea Caforio <[email protected]>
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@andrea-caforio
andrea-caforio committed Nov 29, 2024
1 parent 97dd83a commit 7135d87
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Showing 10 changed files with 220 additions and 106 deletions.
1 change: 1 addition & 0 deletions hw/ip/aes/pre_dv/aes_tb/aes_tb.core
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Expand Up @@ -19,6 +19,7 @@ filesets:
- rtl/aes_tb_pkg.sv
- rtl/aes_tb_reqs.sv
- rtl/aes_tb_c_dpi.sv
- rtl/dv_regs.sv
- rtl/tlul_delayer.sv
- rtl/tlul_adapter_tb_reqs.sv
- rtl/aes_tb.sv
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6 changes: 3 additions & 3 deletions hw/ip/aes/pre_dv/aes_tb/data/gcm_k128_a0_d0.svh
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Expand Up @@ -105,7 +105,7 @@
read_request(AES_DATA_OUT_2_OFFSET), \
read_request(AES_DATA_OUT_3_OFFSET), \
\
/* Read Caliptra-specific register */ \
read_caliptra(CALIPTRA_NAME_0_OFFSET), \
read_caliptra(CALIPTRA_VERSION_0_OFFSET) \
/* Read DV-specific register */ \
read_dv(DV_NAME_0_OFFSET), \
read_dv(DV_VERSION_0_OFFSET) \
};
6 changes: 3 additions & 3 deletions hw/ip/aes/pre_dv/aes_tb/data/gcm_k128_a0_d16.svh
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Expand Up @@ -131,7 +131,7 @@
read_request(AES_DATA_OUT_2_OFFSET), \
read_request(AES_DATA_OUT_3_OFFSET), \
\
/* Read Caliptra-specific register */ \
read_caliptra(CALIPTRA_NAME_0_OFFSET), \
read_caliptra(CALIPTRA_VERSION_0_OFFSET) \
/* Read DV-specific register */ \
read_dv(DV_NAME_0_OFFSET), \
read_dv(DV_VERSION_0_OFFSET) \
};
6 changes: 3 additions & 3 deletions hw/ip/aes/pre_dv/aes_tb/data/gcm_k128_a20_d60.svh
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Expand Up @@ -836,7 +836,7 @@
read_request(AES_DATA_OUT_2_OFFSET), \
read_request(AES_DATA_OUT_3_OFFSET), \
\
/* Read Caliptra-specific register */ \
read_caliptra(CALIPTRA_NAME_0_OFFSET), \
read_caliptra(CALIPTRA_VERSION_0_OFFSET) \
/* Read DV-specific register */ \
read_dv(DV_NAME_0_OFFSET), \
read_dv(DV_VERSION_0_OFFSET) \
};
6 changes: 3 additions & 3 deletions hw/ip/aes/pre_dv/aes_tb/data/gcm_k128_a20_d64.svh
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Expand Up @@ -247,7 +247,7 @@
read_request(AES_DATA_OUT_2_OFFSET), \
read_request(AES_DATA_OUT_3_OFFSET), \
\
/* Read Caliptra-specific register */ \
read_caliptra(CALIPTRA_NAME_0_OFFSET), \
read_caliptra(CALIPTRA_VERSION_0_OFFSET) \
/* Read DV-specific register */ \
read_dv(DV_NAME_0_OFFSET), \
read_dv(DV_VERSION_0_OFFSET) \
};
6 changes: 3 additions & 3 deletions hw/ip/aes/pre_dv/aes_tb/data/modes_d64.svh
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Expand Up @@ -3600,7 +3600,7 @@
read_request(AES_DATA_OUT_3_OFFSET), \
read_request(AES_STATUS_OFFSET, 32'(1'b1) << AES_STATUS_IDLE_OFFSET), \
\
/* Read Caliptra-specific register */ \
read_caliptra(CALIPTRA_NAME_0_OFFSET), \
read_caliptra(CALIPTRA_VERSION_0_OFFSET) \
/* Read DV-specific register */ \
read_dv(DV_NAME_0_OFFSET), \
read_dv(DV_VERSION_0_OFFSET) \
};
112 changes: 79 additions & 33 deletions hw/ip/aes/pre_dv/aes_tb/rtl/aes_tb.sv
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Expand Up @@ -101,11 +101,11 @@ module aes_tb
end

aes_tb_reqs u_aes_tb_reqs (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.pop_req_i ( bus_pop ),
.req_o ( bus_req ),
.done_o ( bus_done )
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.pop_req_i ( bus_pop ),
.req_o ( bus_req ),
.done_o ( bus_done )
);

// Every request that is not a `c_dpi_load` counts as a valid bus access.
Expand All @@ -114,43 +114,89 @@ module aes_tb

// The shim converts inputs from the valid-hold protocol into TLUL requests.
if (ShimEnable) begin : gen_tlul_adapter_shim

logic int_dv;
logic [top_pkg::TL_AW-1:0] int_addr;
logic int_write;
logic [top_pkg::TL_DW-1:0] int_wdata;
logic [top_pkg::TL_DBW-1:0] int_wstrb;
logic [2:0] int_size;
logic int_hld;
logic [top_pkg::TL_DW-1:0] int_rdata;
logic int_error;
logic int_last;
logic [31:0] int_user;
logic [top_pkg::TL_AIW-1:0] int_id;

tlul_adapter_shim #(
.EnableDataIntgGen ( EnableDataIntgGen ),
.EnableRspDataIntgCheck ( EnableRspDataIntgCheck )
) u_tlul_adapter_shim (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.tl_i ( tl_d2h_delayed ),
.tl_o ( tl_h2d ),
.dv_i ( bus_en ),
.addr_i ( bus_req.addr ),
.write_i ( bus_req.write ),
.wdata_i ( bus_req.wdata ),
.wstrb_i ( 4'b1111 ),
.size_i ( 3'b010 ),
.hld_o ( bus_wait ),
.rdata_o ( bus_rdata ),
.error_o ( bus_error ),
.last_i ( 1'b0 ),
.user_i ( 32'(TL_A_USER_DEFAULT) ),
.id_i ( '0 )
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.tl_i ( tl_d2h_delayed ),
.tl_o ( tl_h2d ),
// DV to TLUL
.dv_i ( bus_en ),
.addr_i ( bus_req.addr ),
.write_i ( bus_req.write ),
.wdata_i ( bus_req.wdata ),
.wstrb_i ( 4'b1111 ),
.size_i ( 3'b010 ),
.hld_o ( bus_wait ),
.rdata_o ( bus_rdata ),
.error_o ( bus_error ),
.last_i ( 1'b0 ),
.user_i ( 32'(TL_A_USER_DEFAULT) ),
.id_i ( '0 ),
// DV to internal register
.int_dv_o ( int_dv ),
.int_addr_o ( int_addr ),
.int_write_o ( int_write ),
.int_wdata_o ( int_wdata ),
.int_wstrb_o ( int_wstrb ),
.int_size_o ( int_size ),
.int_hld_i ( int_hld ),
.int_rdata_i ( int_rdata ),
.int_error_i ( int_error ),
.int_last_o ( int_last ),
.int_user_o ( int_user ),
.int_id_o ( int_id )
);

dv_regs u_dv_regs (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.dv_i ( int_dv ),
.addr_i ( int_addr ),
.write_i ( int_write ),
.wdata_i ( int_wdata ),
.wstrb_i ( int_wstrb ),
.size_i ( int_size ),
.hld_o ( int_hld ),
.rdata_o ( int_rdata ),
.error_o ( int_error ),
.last_i ( int_last ),
.user_i ( int_user ),
.id_i ( int_id )
);

end else begin : gen_tlul_adapter
tlul_adapter_tb_reqs #(
.EnableDataIntgGen ( EnableDataIntgGen ),
.EnableRspDataIntgCheck ( EnableRspDataIntgCheck )
) u_tlul_adapter_tb_reqs (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.tl_i ( tl_d2h_delayed ),
.tl_o ( tl_h2d ),
.en_i ( bus_en ),
.wait_o ( bus_wait ),
.addr_i ( bus_req.addr ),
.write_i ( bus_req.write ),
.wdata_i ( bus_req.wdata ),
.rdata_o ( bus_rdata ),
.error_o ( bus_error )
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.tl_i ( tl_d2h_delayed ),
.tl_o ( tl_h2d ),
.en_i ( bus_en ),
.wait_o ( bus_wait ),
.addr_i ( bus_req.addr ),
.write_i ( bus_req.write ),
.wdata_i ( bus_req.wdata ),
.rdata_o ( bus_rdata ),
.error_o ( bus_error )
);
end

Expand Down Expand Up @@ -228,7 +274,7 @@ module aes_tb
end
end

logic [31:0] data_mask;
logic [31:0] data_mask;
assign data_mask = data_cntr_q >= 4 ? 32'hffff_ffff :
data_cntr_q == 3 ? 32'h00ff_ffff :
data_cntr_q == 2 ? 32'h0000_ffff :
Expand Down
18 changes: 9 additions & 9 deletions hw/ip/aes/pre_dv/aes_tb/rtl/aes_tb_pkg.sv
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Expand Up @@ -30,11 +30,11 @@ package aes_tb_pkg;
parameter int AES_TRIGGER_DATA_OUT_CLEAR_OFFSET = 2;
parameter int AES_TRIGGER_PRNG_RESEED_OFFSET = 3;

// Caliptra register offsets
parameter logic [11:0] CALIPTRA_NAME_0_OFFSET = 12'h100;
parameter logic [11:0] CALIPTRA_NAME_1_OFFSET = 12'h104;
parameter logic [11:0] CALIPTRA_VERSION_0_OFFSET = 12'h108;
parameter logic [11:0] CALIPTRA_VERSION_1_OFFSET = 12'h10c;
// DV register offsets
parameter logic [11:0] DV_NAME_0_OFFSET = 12'h100;
parameter logic [11:0] DV_NAME_1_OFFSET = 12'h104;
parameter logic [11:0] DV_VERSION_0_OFFSET = 12'h108;
parameter logic [11:0] DV_VERSION_1_OFFSET = 12'h10c;

`include `REQUESTS_FILE

Expand Down Expand Up @@ -98,10 +98,10 @@ package aes_tb_pkg;
return req;
endfunction

// read_caliptra returns a filled out `bus_request_t` struct for an internal Caliptra register.
// This is only useful if a TLUL-to-Shim adapter is configured otherwise the request will result
// in a zero-value being returned by the register file.
function automatic bus_request_t read_caliptra (logic [11:0] addr);
// read_dv returns a filled out `bus_request_t` struct for an internal register. This is only
// useful if a TLUL-to-Shim adapter is configured otherwise the request will result in a
// zero-value being returned by the register file.
function automatic bus_request_t read_dv (logic [11:0] addr);
bus_request_t req = '{
c_dpi_load: 1'b0,
write: 1'b0,
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60 changes: 60 additions & 0 deletions hw/ip/aes/pre_dv/aes_tb/rtl/dv_regs.sv
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@@ -0,0 +1,60 @@
// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0

// Dummy placeholder module for a DV register file supporting same-cycle reads of name and version
// registers.

module dv_regs
import tlul_pkg::*;
#(
parameter bit [31:0] DV_NAME_0 = 32'hDEADBEEF,
parameter bit [31:0] DV_NAME_1 = 32'hCAFEBABE,
parameter bit [31:0] DV_VERSION_0 = 32'h00000001,
parameter bit [31:0] DV_VERSION_1 = 32'h00000000,

parameter int ADDR_WIDTH = top_pkg::TL_AW,
parameter int DATA_WIDTH = top_pkg::TL_DW,
parameter int MASK_WIDTH = DATA_WIDTH >> 3,
parameter int USER_WIDTH = 32,
parameter int ID_WIDTH = top_pkg::TL_AIW
) (
input clk_i,
input rst_ni,

input logic dv_i,
output logic hld_o,
input logic [ADDR_WIDTH-1:0] addr_i,
input logic write_i,
input logic [DATA_WIDTH-1:0] wdata_i,
input logic [MASK_WIDTH-1:0] wstrb_i,
input logic [2:0] size_i,
output logic [DATA_WIDTH-1:0] rdata_o,
output logic error_o,
// Optional signals
input logic last_i,
input logic [USER_WIDTH-1:0] user_i,
input logic [ID_WIDTH-1:0] id_i
);

always_comb begin
rdata_o = '0;
if (dv_i) begin
unique case (addr_i[3:0])
4'h0: rdata_o = DV_NAME_0;
4'h4: rdata_o = DV_NAME_1;
4'h8: rdata_o = DV_VERSION_0;
4'hc: rdata_o = DV_VERSION_1;
default: rdata_o = '0;
endcase
end
end

assign hld_o = 1'b0;
assign error_o = 1'b0;

logic unused_signals;
assign unused_signals = ^{clk_i, rst_ni, addr_i[31:4], write_i, wdata_i, wstrb_i, size_i, last_i,
user_i, id_i};

endmodule
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