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[tlul, shim] Externalize Caliptra registers #12

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Nov 29, 2024
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[tlul, shim] Externalize Caliptra registers #12

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5 changes: 3 additions & 2 deletions hw/ip/aes/pre_dv/aes_tb/README.md
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@@ -1,9 +1,9 @@
# TLUL/Shim Verilator Testbench
# AES Verilator Testbench

This directory contains the Verilator testbench for the AES IP block.
Out of the box, the testbench contains test vectors for most of the salient use cases, nonetheless extending the testbench with further tests is straightforward as detailed below.
By default, communication with the IP happens over the TLUL bus.
If a TLUL/shim adapter is available, messages can optionally be relayed by the shim.
If a TLUL/Valid-Hold adapter is available, messages can optionally be relayed by the adapter.

## Current Test Vectors

Expand Down Expand Up @@ -53,6 +53,7 @@ To execute the obtained Verilator binary and with trace generation, run:
- rtl/aes\_tb.sv: contains the testbench logic
- rtl/tlul\_delayer.sv: contains an optional delayer module to artificially induce random delays in the TLUL bus.
- rtl/tlul\_adapter_tb_reqs.sv: is an adapter than converts generic read/write requests into TLUL requests.
- rtl/vh\_regs.sv: dummy placeholder module for a Valid-Hold register file.
- rtl/aes\_tb_reqs.sv: contains requests (stimuli) that are fed to the testbench.
- rtl/aes\_tb_pkg.sv: contains common parameters and functions.
- data/*: contains test vector files.
3 changes: 2 additions & 1 deletion hw/ip/aes/pre_dv/aes_tb/aes_tb.core
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Expand Up @@ -9,7 +9,7 @@ filesets:
depend:
- lowrisc:ip:aes
- lowrisc:dv:aes_model_dpi
- lowrisc:tlul:adapter_shim
- lowrisc:tlul:adapter_vh
files:
- data/gcm_k128_a20_d60.svh : {is_include_file : true}
- data/gcm_k128_a20_d64.svh : {is_include_file : true}
Expand All @@ -19,6 +19,7 @@ filesets:
- rtl/aes_tb_pkg.sv
- rtl/aes_tb_reqs.sv
- rtl/aes_tb_c_dpi.sv
- rtl/vh_regs.sv
- rtl/tlul_delayer.sv
- rtl/tlul_adapter_tb_reqs.sv
- rtl/aes_tb.sv
Expand Down
6 changes: 3 additions & 3 deletions hw/ip/aes/pre_dv/aes_tb/data/gcm_k128_a0_d0.svh
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Expand Up @@ -105,7 +105,7 @@
read_request(AES_DATA_OUT_2_OFFSET), \
read_request(AES_DATA_OUT_3_OFFSET), \
\
/* Read Caliptra-specific register */ \
read_caliptra(CALIPTRA_NAME_0_OFFSET), \
read_caliptra(CALIPTRA_VERSION_0_OFFSET) \
/* Read VH-specific register */ \
read_vh(VH_NAME_0_OFFSET), \
read_vh(VH_VERSION_0_OFFSET) \
};
6 changes: 3 additions & 3 deletions hw/ip/aes/pre_dv/aes_tb/data/gcm_k128_a0_d16.svh
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Expand Up @@ -131,7 +131,7 @@
read_request(AES_DATA_OUT_2_OFFSET), \
read_request(AES_DATA_OUT_3_OFFSET), \
\
/* Read Caliptra-specific register */ \
read_caliptra(CALIPTRA_NAME_0_OFFSET), \
read_caliptra(CALIPTRA_VERSION_0_OFFSET) \
/* Read VH-specific register */ \
read_vh(VH_NAME_0_OFFSET), \
read_vh(VH_VERSION_0_OFFSET) \
};
6 changes: 3 additions & 3 deletions hw/ip/aes/pre_dv/aes_tb/data/gcm_k128_a20_d60.svh
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Expand Up @@ -836,7 +836,7 @@
read_request(AES_DATA_OUT_2_OFFSET), \
read_request(AES_DATA_OUT_3_OFFSET), \
\
/* Read Caliptra-specific register */ \
read_caliptra(CALIPTRA_NAME_0_OFFSET), \
read_caliptra(CALIPTRA_VERSION_0_OFFSET) \
/* Read VH-specific register */ \
read_vh(VH_NAME_0_OFFSET), \
read_vh(VH_VERSION_0_OFFSET) \
};
6 changes: 3 additions & 3 deletions hw/ip/aes/pre_dv/aes_tb/data/gcm_k128_a20_d64.svh
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Expand Up @@ -247,7 +247,7 @@
read_request(AES_DATA_OUT_2_OFFSET), \
read_request(AES_DATA_OUT_3_OFFSET), \
\
/* Read Caliptra-specific register */ \
read_caliptra(CALIPTRA_NAME_0_OFFSET), \
read_caliptra(CALIPTRA_VERSION_0_OFFSET) \
/* Read VH-specific register */ \
read_vh(VH_NAME_0_OFFSET), \
read_vh(VH_VERSION_0_OFFSET) \
};
6 changes: 3 additions & 3 deletions hw/ip/aes/pre_dv/aes_tb/data/modes_d64.svh
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Expand Up @@ -3600,7 +3600,7 @@
read_request(AES_DATA_OUT_3_OFFSET), \
read_request(AES_STATUS_OFFSET, 32'(1'b1) << AES_STATUS_IDLE_OFFSET), \
\
/* Read Caliptra-specific register */ \
read_caliptra(CALIPTRA_NAME_0_OFFSET), \
read_caliptra(CALIPTRA_VERSION_0_OFFSET) \
/* Read VH-specific register */ \
read_vh(VH_NAME_0_OFFSET), \
read_vh(VH_VERSION_0_OFFSET) \
};
122 changes: 84 additions & 38 deletions hw/ip/aes/pre_dv/aes_tb/rtl/aes_tb.sv
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Expand Up @@ -19,7 +19,7 @@ module aes_tb
localparam bit EnableDataIntgGen = 1,
localparam bit EnableRspDataIntgCheck = 1,
localparam bit DelayerEnable = 0,
localparam bit ShimEnable = 1
localparam bit ValidHoldEnable = 1
) (
input logic clk_i,
input logic rst_ni,
Expand Down Expand Up @@ -101,56 +101,102 @@ module aes_tb
end

aes_tb_reqs u_aes_tb_reqs (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.pop_req_i ( bus_pop ),
.req_o ( bus_req ),
.done_o ( bus_done )
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.pop_req_i ( bus_pop ),
.req_o ( bus_req ),
.done_o ( bus_done )
);

// Every request that is not a `c_dpi_load` counts as a valid bus access.
logic bus_en;
assign bus_en = ~bus_req.c_dpi_load;

// The shim converts inputs from the valid-hold protocol into TLUL requests.
if (ShimEnable) begin : gen_tlul_adapter_shim
tlul_adapter_shim #(
// The Valid-Hold adapter converts inputs from the valid-hold protocol into TLUL requests.
if (ValidHoldEnable) begin : gen_tlul_adapter_vh

logic int_dv;
logic [top_pkg::TL_AW-1:0] int_addr;
logic int_write;
logic [top_pkg::TL_DW-1:0] int_wdata;
logic [top_pkg::TL_DBW-1:0] int_wstrb;
logic [2:0] int_size;
logic int_hld;
logic [top_pkg::TL_DW-1:0] int_rdata;
logic int_error;
logic int_last;
logic [31:0] int_user;
logic [top_pkg::TL_AIW-1:0] int_id;

tlul_adapter_vh #(
.EnableDataIntgGen ( EnableDataIntgGen ),
.EnableRspDataIntgCheck ( EnableRspDataIntgCheck )
) u_tlul_adapter_shim (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.tl_i ( tl_d2h_delayed ),
.tl_o ( tl_h2d ),
.dv_i ( bus_en ),
.addr_i ( bus_req.addr ),
.write_i ( bus_req.write ),
.wdata_i ( bus_req.wdata ),
.wstrb_i ( 4'b1111 ),
.size_i ( 3'b010 ),
.hld_o ( bus_wait ),
.rdata_o ( bus_rdata ),
.error_o ( bus_error ),
.last_i ( 1'b0 ),
.user_i ( 32'(TL_A_USER_DEFAULT) ),
.id_i ( '0 )
) u_tlul_adapter_vh (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.tl_i ( tl_d2h_delayed ),
.tl_o ( tl_h2d ),
// Valid-Hold to TLUL
.dv_i ( bus_en ),
.addr_i ( bus_req.addr ),
.write_i ( bus_req.write ),
.wdata_i ( bus_req.wdata ),
.wstrb_i ( 4'b1111 ),
.size_i ( 3'b010 ),
.hld_o ( bus_wait ),
.rdata_o ( bus_rdata ),
.error_o ( bus_error ),
.last_i ( 1'b0 ),
.user_i ( 32'(TL_A_USER_DEFAULT) ),
.id_i ( '0 ),
// Valid-Hold to internal register
.int_dv_o ( int_dv ),
.int_addr_o ( int_addr ),
.int_write_o ( int_write ),
.int_wdata_o ( int_wdata ),
.int_wstrb_o ( int_wstrb ),
.int_size_o ( int_size ),
.int_hld_i ( int_hld ),
.int_rdata_i ( int_rdata ),
.int_error_i ( int_error ),
.int_last_o ( int_last ),
.int_user_o ( int_user ),
.int_id_o ( int_id )
);

vh_regs u_vh_regs (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.dv_i ( int_dv ),
.addr_i ( int_addr ),
.write_i ( int_write ),
.wdata_i ( int_wdata ),
.wstrb_i ( int_wstrb ),
.size_i ( int_size ),
.hld_o ( int_hld ),
.rdata_o ( int_rdata ),
.error_o ( int_error ),
.last_i ( int_last ),
.user_i ( int_user ),
.id_i ( int_id )
);

end else begin : gen_tlul_adapter
tlul_adapter_tb_reqs #(
.EnableDataIntgGen ( EnableDataIntgGen ),
.EnableRspDataIntgCheck ( EnableRspDataIntgCheck )
) u_tlul_adapter_tb_reqs (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.tl_i ( tl_d2h_delayed ),
.tl_o ( tl_h2d ),
.en_i ( bus_en ),
.wait_o ( bus_wait ),
.addr_i ( bus_req.addr ),
.write_i ( bus_req.write ),
.wdata_i ( bus_req.wdata ),
.rdata_o ( bus_rdata ),
.error_o ( bus_error )
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.tl_i ( tl_d2h_delayed ),
.tl_o ( tl_h2d ),
.en_i ( bus_en ),
.wait_o ( bus_wait ),
.addr_i ( bus_req.addr ),
.write_i ( bus_req.write ),
.wdata_i ( bus_req.wdata ),
.rdata_o ( bus_rdata ),
.error_o ( bus_error )
);
end

Expand Down Expand Up @@ -228,7 +274,7 @@ module aes_tb
end
end

logic [31:0] data_mask;
logic [31:0] data_mask;
assign data_mask = data_cntr_q >= 4 ? 32'hffff_ffff :
data_cntr_q == 3 ? 32'h00ff_ffff :
data_cntr_q == 2 ? 32'h0000_ffff :
Expand Down
2 changes: 1 addition & 1 deletion hw/ip/aes/pre_dv/aes_tb/rtl/aes_tb_c_dpi.sv
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Expand Up @@ -9,8 +9,8 @@

module aes_tb_c_dpi
import aes_pkg::*;
import aes_tb_pkg::*;
import aes_model_dpi_pkg::*;
import aes_tb_pkg::*;
#(
parameter int ADLength = 0,
parameter int DataLength = 16
Expand Down
26 changes: 13 additions & 13 deletions hw/ip/aes/pre_dv/aes_tb/rtl/aes_tb_pkg.sv
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Expand Up @@ -30,11 +30,11 @@ package aes_tb_pkg;
parameter int AES_TRIGGER_DATA_OUT_CLEAR_OFFSET = 2;
parameter int AES_TRIGGER_PRNG_RESEED_OFFSET = 3;

// Caliptra register offsets
parameter logic [11:0] CALIPTRA_NAME_0_OFFSET = 12'h100;
parameter logic [11:0] CALIPTRA_NAME_1_OFFSET = 12'h104;
parameter logic [11:0] CALIPTRA_VERSION_0_OFFSET = 12'h108;
parameter logic [11:0] CALIPTRA_VERSION_1_OFFSET = 12'h10c;
// Valid-Hold register offsets
parameter logic [11:0] VH_NAME_0_OFFSET = 12'h100;
parameter logic [11:0] VH_NAME_1_OFFSET = 12'h104;
parameter logic [11:0] VH_VERSION_0_OFFSET = 12'h108;
parameter logic [11:0] VH_VERSION_1_OFFSET = 12'h10c;

`include `REQUESTS_FILE

Expand All @@ -53,14 +53,14 @@ package aes_tb_pkg;
logic [127:0] tag; // Only used in the GCM decryption case.
} c_dpi_input_t;

// Grouping of all signals required for a TLUL/shim read/write request and to instrument the
// Grouping of all signals required for a TLUL/VH read/write request and to instrument the
// `c_dpi` API.
typedef struct packed {
logic write;
logic [top_pkg::TL_AW-1:0] addr;
logic [top_pkg::TL_DW-1:0] wdata;

// Internal signal: The request is a `c_dpi` invocation instead of a TLUL/shim request.
// Internal signal: The request is a `c_dpi` invocation instead of a TLUL/VH request.
logic c_dpi_load;

// Internal signal: To mask read request responses, e.g., to check whether a certain bit is set.
Expand All @@ -70,7 +70,7 @@ package aes_tb_pkg;
c_dpi_input_t c_dpi_input;
} bus_request_t;

// write_request returns a filled out `bus_request_t` struct for a TLUL/shim write request.
// write_request returns a filled out `bus_request_t` struct for a TLUL/VH write request.
function automatic bus_request_t write_request (logic [7:0] addr,
logic [top_pkg::TL_DW-1:0] wdata);
bus_request_t req = '{
Expand All @@ -84,7 +84,7 @@ package aes_tb_pkg;
return req;
endfunction

// read_request returns a filled out `bus_request_t` struct for a TLUL/shim read request.
// read_request returns a filled out `bus_request_t` struct for a TLUL/VH read request.
function automatic bus_request_t read_request (logic [7:0] addr,
logic [top_pkg::TL_DW-1:0] mask = '0);
bus_request_t req = '{
Expand All @@ -98,10 +98,10 @@ package aes_tb_pkg;
return req;
endfunction

// read_caliptra returns a filled out `bus_request_t` struct for an internal Caliptra register.
// This is only useful if a TLUL-to-Shim adapter is configured otherwise the request will result
// in a zero-value being returned by the register file.
function automatic bus_request_t read_caliptra (logic [11:0] addr);
// read_vh returns a filled out `bus_request_t` struct for an internal register. This is only
// useful if a TLUL-to-VH adapter is configured otherwise the request will result in a zero-value
// being returned by the register file.
function automatic bus_request_t read_vh (logic [11:0] addr);
bus_request_t req = '{
c_dpi_load: 1'b0,
write: 1'b0,
Expand Down
3 changes: 0 additions & 3 deletions hw/ip/aes/pre_dv/aes_tb/rtl/aes_tb_reqs.sv
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Expand Up @@ -3,9 +3,6 @@
// SPDX-License-Identifier: Apache-2.0

module aes_tb_reqs
import aes_pkg::*;
import aes_reg_pkg::*;
import tlul_pkg::*;
import aes_tb_pkg::*;
(
input logic clk_i,
Expand Down
6 changes: 3 additions & 3 deletions hw/ip/aes/pre_dv/aes_tb/rtl/tlul_adapter_tb_reqs.sv
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Expand Up @@ -51,9 +51,9 @@ module tlul_adapter_tb_reqs
end
end

// Only make a new request (through `a_valid`) to the device when none are
// pending. If the integrity checks are enabled, the `a_user` fields will be
// set by the corresponding module (see `tlul_cmd_intg_gen`).
// Only make a new request (through `a_valid`) to the device when none are pending. If the
// integrity checks are enabled, the `a_user` fields will be set by the corresponding module
// (see `tlul_cmd_intg_gen`).
tlul_pkg::tl_h2d_t tl_o_pre;
assign tl_o_pre = '{
a_valid: en_i & ~pending_q,
Expand Down
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