Skip to content

Commit

Permalink
Fix peripherals base address.
Browse files Browse the repository at this point in the history
  • Loading branch information
Yvan Tortorella committed Jan 20, 2024
1 parent ed1e468 commit 2a5bb10
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion hw/carfield_cfg_pkg.sv
Original file line number Diff line number Diff line change
Expand Up @@ -199,7 +199,7 @@ localparam islands_cfg_t CarfieldIslandsCfg = '{
l2_port1: '{1, 'h78200000, 'h00200000},
safed: '{1, 'h60000000, 'h00800000},
ethernet: '{1, 'h20000000, 'h00001000},
periph: '{1, 'h20010000, 'h00009000},
periph: '{1, 'h20001000, 'h00009000},
spatz: '{1, 'h51000000, 'h00800000},
pulp: '{1, 'h50000000, 'h00800000},
secured: '{1, '1, '1 }, // We do not address opentitan, base address and size are not used.

Check warning on line 205 in hw/carfield_cfg_pkg.sv

View workflow job for this annotation

GitHub Actions / verible-verilog-lint

[verible-verilog-lint] hw/carfield_cfg_pkg.sv#L205

Line length exceeds max: 100; is: 109 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 109 [Style: line-length] [line-length]"  location:{path:"hw/carfield_cfg_pkg.sv"  range:{start:{line:205  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
Expand Down

0 comments on commit 2a5bb10

Please sign in to comment.