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1. carfield carfield Public

   A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.

   Tcl 91 17

2. pulpissimo pulpissimo Public

   This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

   SystemVerilog 416 175

3. cheshire cheshire Public

   A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

   Verilog 247 63

4. snitch_cluster snitch_cluster Public

   An energy-efficient RISC-V floating-point compute cluster.

   C 73 61

5. axi axi Public

   AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

   SystemVerilog 1.3k 286

6. ara ara Public

   The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

   C 418 144