flavor_bd: Adding first bd for VCU118

pulp-platform · Jan 19, 2024 · 07c3ef6 · 07c3ef6
1 parent 964e07b
commit 07c3ef6
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Showing 4 changed files with 50 additions and 5 deletions.
diff --git a/target/xilinx/flavor_bd/constraints/vcu118.xdc b/target/xilinx/flavor_bd/constraints/vcu118.xdc
@@ -0,0 +1,37 @@
+# VIOs are asynchronous
+set_false_path -through [get_pins -of_objects [get_cells design_1_i/vio_0] -filter {NAME =~ *probe*}]
+
+# Create system clocks
+create_clock -period 4 -name sys_clk [get_pins design_1_i/util_ds_buf_0/IBUF_OUT]
+set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins design_1_i/util_ds_buf_0/IBUF_OUT]
+create_clock -period 4 -name pcie_clk [get_nets design_1_i/util_ds_buf_1/U0/IBUF_OUT[0]]
+create_clock -period 4 -name pcie_clk_div [get_nets design_1_i/util_ds_buf_1/U0/IBUF_DS_ODIV2[0]]
+set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets design_1_i/util_ds_buf_1/U0/IBUF_DS_ODIV2[0]]
+set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets design_1_i/util_ds_buf_1/U0/IBUF_OUT[0]]
+
+# PCIe clock LOC
+#set_property LOC [get_package_pins -of_objects [get_bels [get_sites -filter {NAME =~ *COMMON*} -of_objects [get_iobanks -of_objects [get_sites GTYE4_CHANNEL_X1Y15]]]/REFCLK0P]] [get_ports pcie_refclk_clk_p[0]]
+#set_property LOC [get_package_pins -of_objects [get_bels [get_sites -filter {NAME =~ *COMMON*} -of_objects [get_iobanks -of_objects [get_sites GTYE4_CHANNEL_X1Y15]]]/REFCLK0N]] [get_ports pcie_refclk_clk_n[0]]
+
+#  VCU128 Rev1.0 XDC
+#  Date: 01/24/2018
+
+#### This file is a general .xdc for the VCU128 1 Rev.
+#### To use it in a project:
+#### - uncomment the lines corresponding to used pins
+#### - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+set_property PACKAGE_PIN AW25     [get_ports "uart_rx_i"] ;# Bank  67 VCCO - VCC1V8   - IO_L2N_T0L_N3_67
+set_property IOSTANDARD  LVCMOS18 [get_ports "uart_rx_i"] ;# Bank  67 VCCO - VCC1V8   - IO_L2N_T0L_N3_67
+set_property PACKAGE_PIN BB21     [get_ports "uart_tx_o"] ;# Bank  67 VCCO - VCC1V8   - IO_L2P_T0L_N2_67
+set_property IOSTANDARD  LVCMOS18 [get_ports "uart_tx_o"] ;# Bank  67 VCCO - VCC1V8   - IO_L2P_T0L_N2_67
+
+set_property PACKAGE_PIN L19 [get_ports cpu_reset]
+set_property IOSTANDARD LVCMOS12 [get_ports cpu_reset]
+
+#set_property BOARD_PART_PIN default_250mhz_clk_n [get_ports sys_clk_clk_n[0]]
+#set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_clk_n[0]]
+#set_property BOARD_PART_PIN default_100mhz_clk_p [get_ports sys_clk_clk_p[0]]
+#set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_clk_p[0]]
+#set_property PACKAGE_PIN BH51 [get_ports sys_clk_clk_p[0]]
+#set_property PACKAGE_PIN BJ51 [get_ports sys_clk_clk_n[0]]
diff --git a/target/xilinx/flavor_bd/constraints/vcu118_ext_jtag.xdc b/target/xilinx/flavor_bd/constraints/vcu118_ext_jtag.xdc
@@ -0,0 +1,12 @@
+
+set_property PACKAGE_PIN N30     [get_ports jtag_tdo_o] ;# B25 - H17 (FMCP_HSPC_LA11_N) - J1.08 - TDO
+set_property IOSTANDARD LVCMOS33 [get_ports jtag_tdo_o]
+
+set_property PACKAGE_PIN P30     [get_ports jtag_tck_i] ;# B26 - H16 (FMCP_HSPC_LA11_P) - J1.06 - TCK
+set_property IOSTANDARD LVCMOS33 [get_ports jtag_tck_i] ;
+
+set_property PACKAGE_PIN N28     [get_ports jtag_tms_i] ;# H22 - G16 (FMCP_HSPC_LA12_N) - J1.12 - TNS
+set_property IOSTANDARD LVCMOS33 [get_ports jtag_tms_i] ;
+
+set_property PACKAGE_PIN M30     [get_ports jtag_tdi_i] ;# J22 - G15 (FMCP_HSPC_LA12_P) - J1.10 - TDI
+set_property IOSTANDARD LVCMOS33 [get_ports jtag_tdi_i]
diff --git a/target/xilinx/flavor_bd/scripts/carfield_bd_ext_jtag.tcl b/target/xilinx/flavor_bd/scripts/carfield_bd_ext_jtag.tcl
@@ -4,15 +4,11 @@
 #
 # Cyril Koenig <[email protected]>
 
-set jtag_gnd_o [ create_bd_port -dir O jtag_gnd_o ]
 set jtag_tck_i [ create_bd_port -dir I jtag_tck_i ]
 set jtag_tdi_i [ create_bd_port -dir I jtag_tdi_i ]
 set jtag_tdo_o [ create_bd_port -dir O jtag_tdo_o ]
 set jtag_tms_i [ create_bd_port -dir I jtag_tms_i ]
-set jtag_vdd_o [ create_bd_port -dir O jtag_vdd_o ]
-connect_bd_net -net carfield_xilinx_ip_0_jtag_gnd_o [get_bd_ports jtag_gnd_o] [get_bd_pins carfield_xilinx_ip_0/jtag_gnd_o]
 connect_bd_net -net carfield_xilinx_ip_0_jtag_tdo_o [get_bd_ports jtag_tdo_o] [get_bd_pins carfield_xilinx_ip_0/jtag_tdo_o]
-connect_bd_net -net carfield_xilinx_ip_0_jtag_vdd_o [get_bd_ports jtag_vdd_o] [get_bd_pins carfield_xilinx_ip_0/jtag_vdd_o]
 connect_bd_net -net jtag_tck_i_1 [get_bd_ports jtag_tck_i] [get_bd_pins carfield_xilinx_ip_0/jtag_tck_i]
 connect_bd_net -net jtag_tdi_i_1 [get_bd_ports jtag_tdi_i] [get_bd_pins carfield_xilinx_ip_0/jtag_tdi_i]
 connect_bd_net -net jtag_tms_i_1 [get_bd_ports jtag_tms_i] [get_bd_pins carfield_xilinx_ip_0/jtag_tms_i]
diff --git a/target/xilinx/xilinx_ips/carfield_ip/tcl/run.tcl b/target/xilinx/xilinx_ips/carfield_ip/tcl/run.tcl
@@ -26,7 +26,7 @@ set_property top carfield_xilinx_ip [current_fileset]
 
 # Attention SFCU is only used because of Carfield's structure
 update_compile_order -fileset sources_1
-synth_design -rtl -name rtl_1 -sfcu
+#synth_design -rtl -name rtl_1 -sfcu
 
 ipx::package_project -root_dir . -vendor ethz.ch -library user -taxonomy /UserIP -set_current false