flavor_vanilla: Auto gen of Vivado example

pulp-platform · Jan 18, 2024 · 964e07b · 964e07b
1 parent 468ad6b
commit 964e07b
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Showing 5 changed files with 101 additions and 25 deletions.
diff --git a/target/xilinx/flavor_vanilla/.gitignore b/target/xilinx/flavor_vanilla/.gitignore
@@ -1,6 +1,5 @@
 .Xil
-carfield.*
 scripts/add_sources.tcl*
 scripts/add_includes.tcl
 out/
-probes.ltx
+probes.ltx
diff --git a/target/xilinx/flavor_vanilla/sim/run_simulation.tcl b/target/xilinx/flavor_vanilla/sim/run_simulation.tcl
@@ -6,25 +6,24 @@
 
 source add_sources.tcl
 
-#if {[string first "xlnx_clk_wiz" $::env(IPS)] != -1} {
-#    source ips/xlnx_clk_wiz/questa/compile.do
-#
-#if {[string first "xlnx_vio" $::env(IPS)] != -1} {
-#    source ips/xlnx_vio/questa/compile.do
-#}}
-#
-#if {[string first "xlnx_mig_7_ddr3" $::env(IPS)] != -1} {
-#    source ips/xlnx_mig_7_ddr3_ex/questa/compile.do
-#    source ips/xlnx_mig_7_ddr3/questa/compile.do
-#    vlog -work work -L xil_defaultlib -64 -incr -sv "./ips/xlnx_mig_7_ddr3_ex/questa/srcs/sim_tb_top.v"
-#}
-#
-#if {[string first "xlnx_mig_ddr4" $::env(IPS)] != -1} {
-#    source ips/xlnx_mig_ddr4_ex/questa/compile.do
-#    source ips/xlnx_mig_ddr4/questa/compile.do
-#    vlog -work work -L xil_defaultlib -64 -incr -sv "./ips/xlnx_mig_ddr4_ex/questa/srcs/sim_tb_top.sv"
-#}
-#
+if {[string first "xlnx_clk_wiz" $::env(IPS)] != -1} {
+    source ips/xlnx_clk_wiz/questa/compile.do
+
+if {[string first "xlnx_vio" $::env(IPS)] != -1} {
+    source ips/xlnx_vio/questa/compile.do
+}}
+
+if {[string first "xlnx_mig_7_ddr3" $::env(IPS)] != -1} {
+    source ips/xlnx_mig_7_ddr3_ex/questa/compile.do
+    source ips/xlnx_mig_7_ddr3/questa/compile.do
+}
+
+if {[string first "xlnx_mig_ddr4" $::env(IPS)] != -1} {
+    source ips/xlnx_mig_ddr4_ex/questa/compile.do
+    source ips/xlnx_mig_ddr4/questa/compile.do
+    vlog -work work ips/xlnx_mig_ddr4_ex/imports/sim_tb_top.sv -L xil_defaultlib
+}
+
 ## Note : this testbench does not implenent the ddr4 memory model
 set TESTBENCH "work.sim_tb_top xil_defaultlib.glbl"
 
@@ -45,4 +44,4 @@ if {[info exists IMAGE]}    { append pargs "+IMAGE=${IMAGE} " }
 eval "vsim ${TESTBENCH} -t 1ps -vopt -voptargs=\"${VOPTARGS}\"" ${XLIB_ARGS} ${pargs} ${flags}
 
 set StdArithNoWarnings 1
-set NumericStdNoWarnings 1
+set NumericStdNoWarnings 1
diff --git a/target/xilinx/flavor_vanilla/sim/setup_simulation.tcl b/target/xilinx/flavor_vanilla/sim/setup_simulation.tcl
@@ -26,6 +26,18 @@ if { $command == "compile_simlib" } {
   export_simulation -simulator questa -directory "./ips" -lib_map_path "$::env(XILINX_SIMLIB_PATH)" \
     -absolute_path -force -of_objects [get_ips *]
 
+# Export simulation scripts for each ip
+} elseif { $command == "export_example" } {
+  open_project $::env(VIVADO_PROJECT)
+  open_example_project -dir "./ips" -force [get_ips xlnx_mig_ddr4]
+
+# Export simulation scripts for each ip
+} elseif { $command == "export_example_simulation" } {
+  open_project $::env(VIVADO_PROJECT)
+  export_simulation -lib_map_path "$::env(XILINX_SIMLIB_PATH)" -directory "." -simulator questa \
+    -ip_user_files_dir "./ips/xlnx_mig_ddr4_ex/xlnx_mig_ddr4_ex.ip_user_files" \
+    -ipstatic_source_dir "./ips/xlnx_mig_ddr4_ex/xlnx_mig_ddr4_ex.ip_user_files/ipstatic" -use_ip_compiled_libs -directory "./ips/xlnx_mig_ddr4_ex/" -absolute_path
+
 # Unknown command
 } else {
   puts "[$argv0] Unknown command: $command"

diff --git a/target/xilinx/flavor_vanilla/sim/sim.mk b/target/xilinx/flavor_vanilla/sim/sim.mk
@@ -33,7 +33,12 @@ car-xil-vlog-args := -suppress 2583 -suppress 13314
 # Fetch example projects at IIS (containing SRAM behavioral models)
 $(CAR_XIL_SIM_DIR)/ips/%_ex/questa/compile.do:
 	mkdir -p $(CAR_XIL_SIM_DIR)/ips
-	tar -xvf /usr/scratch2/wuerzburg/cykoenig/export/$*_ex.tar -C $(CAR_XIL_SIM_DIR)/ips
+	# First the example project
+	cd $(CAR_XIL_SIM_DIR) && $(vivado_env_sim) $(VIVADO) -nojournal -mode batch -source setup_simulation.tcl -tclargs "export_example"
+	# Then the example simulation
+	cd $(CAR_XIL_SIM_DIR) && $(vivado_env_sim) VIVADO_PROJECT=$(CAR_XIL_DIR)/flavor_vanilla/sim/ips/xlnx_mig_ddr4_ex/xlnx_mig_ddr4_ex.xpr $(VIVADO) -nojournal -mode batch -source setup_simulation.tcl -tclargs "export_example_simulation"
+	# Replace the DUT with carfield top
+	patch $(CAR_XIL_SIM_DIR)/ips/xlnx_mig_ddr4_ex/imports/sim_tb_top.sv $(CAR_XIL_SIM_DIR)/sim_tb_top.diff
 
 # Generate generic Xilinx simulation libraries
 $(CAR_XIL_SIM_SIMLIB_PATH)/modelsim.ini:
@@ -53,10 +58,10 @@ car-xil-sim: $(CAR_XIL_DIR)/flavor_vanilla/carfield.xpr $(CAR_XIL_SIM_SIMLIB_PAT
 	mkdir -p $(CAR_XIL_SIM_DIR)/questa_lib
 	cp $(CAR_XIL_SIM_SIMLIB_PATH)/modelsim.ini $(CAR_XIL_SIM_DIR)
 	chmod +w $(CAR_XIL_SIM_DIR)/modelsim.ini
-	cd $(CAR_XIL_SIM_DIR) && IPS="$(xilinx_ips_names_vanilla)" questa-2022.3 vsim -work work -do "run_simulation.tcl"
+	cd $(CAR_XIL_SIM_DIR) && BOARD="$(XILINX_BOARD)" IPS="$(xilinx_ips_names_vanilla)" questa-2022.3 vsim -work work -do "run_simulation.tcl"
 
 # Clean
 car-xil-sim-clean:
 	cd $(CAR_XIL_SIM_DIR) && rm -rf *.log questa_lib work transcript vsim.wlf add_sources.tcl .Xil modelsim.ini ips
 
-.PHONY: clean-sim sim
+.PHONY: clean-sim sim
diff --git a/target/xilinx/flavor_vanilla/sim/sim_tb_top.diff b/target/xilinx/flavor_vanilla/sim/sim_tb_top.diff
@@ -0,0 +1,61 @@
+217,220c217,244
+<   example_top 
+<     u_example_top
+<     (
+<      .sys_rst           (sys_rst),
+---
+> logic         cpu_reset;
+> logic         cpu_resetn;
+> logic         sys_clk_p;
+> logic         sys_clk_n;
+> logic         testmode_i;
+> logic [1:0]   boot_mode_i;
+> logic         jtag_tck_i;
+> logic         jtag_tms_i;
+> logic         jtag_tdi_i;
+> logic         jtag_tdo_o;
+> logic         jtag_trst_ni;
+> logic         jtag_vdd_o;
+> logic         jtag_gnd_o;
+> logic         uart_tx_o;
+> logic         uart_rx_i;
+> 
+> assign cpu_reset = sys_rst;
+> assign cpu_resetn = ~cpu_reset;
+> assign boot_mode_i = '0;
+> assign testmode_i = '0;
+> assign jtag_tck_i = '0;
+> assign jtag_tms_i = '0;
+> assign jtag_tdi_i = '0;
+> assign jtag_trst_ni = '0;
+> assign uart_rx_i = '0;
+> 
+> assign sys_clk_p = c0_sys_clk_p;
+> assign sys_clk_n = c0_sys_clk_n;
+222,241c248,252
+<      .c0_data_compare_error  (c0_data_compare_error),
+<      .c0_init_calib_complete (c0_init_calib_complete),
+<      .c0_sys_clk_p           (c0_sys_clk_p),
+<      .c0_sys_clk_n           (c0_sys_clk_n),
+< 
+<      .c0_ddr4_act_n          (c0_ddr4_act_n),
+<      .c0_ddr4_adr            (c0_ddr4_adr),
+<      .c0_ddr4_ba             (c0_ddr4_ba),
+<      .c0_ddr4_bg             (c0_ddr4_bg),
+<      .c0_ddr4_cke            (c0_ddr4_cke),
+<      .c0_ddr4_odt            (c0_ddr4_odt),
+<      .c0_ddr4_cs_n           (c0_ddr4_cs_n),
+<      .c0_ddr4_ck_t           (c0_ddr4_ck_t_int),
+<      .c0_ddr4_ck_c           (c0_ddr4_ck_c_int),
+<      .c0_ddr4_reset_n        (c0_ddr4_reset_n),
+<      .c0_ddr4_dm_dbi_n       (c0_ddr4_dm_dbi_n),
+<      .c0_ddr4_dq             (c0_ddr4_dq),
+<      .c0_ddr4_dqs_c          (c0_ddr4_dqs_c),
+<      .c0_ddr4_dqs_t          (c0_ddr4_dqs_t)
+<      );
+---
+>   carfield_top_xilinx 
+>     u_carfield_top_xilinx
+>     (
+>      .*
+>     );