Skip to content

Navigation Menu

Explore
By company size
By use case
By industry
View all solutions
Topics
- AI
- DevOps
- Security
- Software Development
- View all
Explore
- GitHub Sponsors
  Fund open source developers
- The ReadME Project
  GitHub community articles
Repositories
- Enterprise platform
  AI-powered developer platform
Available add-ons
Pricing

Search code, repositories, users, issues, pull requests...

Search

Clear

Search syntax tips

Provide feedback

We read every piece of feedback, and take your input very seriously.

Include my email address so I can be contacted

Saved searches

Use saved searches to filter your results more quickly

Name

Query

To see all available qualifiers, see our documentation.

You signed in with another tab or window. Reload to refresh your session. You signed out in another tab or window. Reload to refresh your session. You switched accounts on another tab or window. Reload to refresh your session.

Dismiss alert

eddieh-xlnx / fpga24_routing_contest Public

forked from Xilinx/fpga24_routing_contest

Notifications You must be signed in to change notification settings
Fork 0
Star 0

Code
Pull requests
Actions
Security
Insights

Additional navigation options

Code
Pull requests
Actions
Security
Insights

[pull] master from Xilinx:master#7

Merged

pull[bot] merged 2 commits intoeddieh-xlnx:mastereddieh-xlnx/fpga24_routing_contest:masterfrom Xilinx:masterXilinx/fpga24_routing_contest:masterCopy head branch name to clipboard

Oct 31, 2023

+29-17

Conversation Commits2 (2)Checks Files changed

Commits

Commits on Oct 31, 2023

PIP Clarifications (#33 )

zakn-amd
and
eddieh-xlnx
authored
wirelength_analyzer to check PIP tile before assigning zero WL (#34 )
eddieh-xlnx
authored

Footer

© 2025 GitHub, Inc.

Footer navigation

Terms
Privacy
Security
Status
Docs
Contact

You can’t perform that action at this time.