[pull] master from Xilinx:master #7
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* Update scoring page to mention interconnect tiles Signed-off-by: Zak Nafziger <[email protected]> * reword for clarity Co-authored-by: eddieh-xlnx <[email protected]> * move comment about pips only to details page Signed-off-by: Zak Nafziger <[email protected]> * less technical language in initial explanation Co-authored-by: eddieh-xlnx <[email protected]> * update Router section of details Signed-off-by: Zak Nafziger <[email protected]> * improve specificity in details Co-authored-by: eddieh-xlnx <[email protected]> * Mention INT prefix ahead of table * further wording changes Co-authored-by: eddieh-xlnx <[email protected]> --------- Signed-off-by: Zak Nafziger <[email protected]> Co-authored-by: eddieh-xlnx <[email protected]>
* wirelength_analyzer to check PIP tile before assigning zero WL Signed-off-by: Eddie Hung <[email protected]> * Be more strict with 'INT_' prefix Signed-off-by: Eddie Hung <[email protected]> * Add more tile names for in-context ispd16_example2 Signed-off-by: Eddie Hung <[email protected]> * Rename variable Signed-off-by: Eddie Hung <[email protected]> --------- Signed-off-by: Eddie Hung <[email protected]>
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