Runtime-First FPGA Interchange Routing Contest @ FPGA’24

Please see website at https://xilinx.github.io/fpga24_routing_contest.

ℹ️ NOTE:	This contest has now concluded! Link to the results and details from our top 5 teams.

Please report all issues using the GitHub Issues feature, and ask questions under Discussions.

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All content in this repository, except for third-party software otherwise attributed (e.g. Gradle, benchmark assets, etc.) is licensed under:

SPDX-License-Identifier: MIT

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Utilities:

• net_printer -- inspect the routing of nets in a Physical Netlist.
• DcpToFPGAIF -- process a DCP into FPGAIF Logical and Physical Netlists for use with this contest.
• wirelength_analyzer -- compute a critical-path wirelength for a routed FPGAIF Physical Netlist.
• DiffPhysNetlist -- display any illegal differences (placement, intra-site routing, global/static inter-site routing) between two FPGAIF Physical Netlists.