Remove embedded ClockGen in TestBench

[FanShupei]

Proposed Design

This PR proposes we should try move simulation control logic (clock gen, dump wave, watch dog, etc) to TestDriver.sv. These features are inherently coupled with simulation platform. For VCS flow, it's best to address these in verilog code.

Current Design:

module TestBench; // top module, defined in Chisel
  ClockGen clockGen(.clock, .reset); // inlined in Chisel
endmodule

Proposed Design:

module TestDrvier; // top module, defined in sv
  // clock gen logic
  TestBench tb(.clock, .reset);
endmodule

module TestBench(input clock, input reset); // defined in Chisel
endmodule

Benefits

• rapid iteration cycle: currently touch everything in ClockGen requires re-elaboration, which is painfully slow.
• extensible to Arcilator in the future: I suppose we need a dedicated test driver for arc anyway, it's very unlike to reuse current ClockGen.

Future work: I plan do refacoring of simulation control code, the current code is too messy. This is the first step.

UPDATE: After discusssion, we reach consensus that no need to pull inner ClockGen to outer TestDriver. This PR only change inlined ClockGen to ExtModule.

[sequencer]

Does verilator work now.