[rtl] add token manager for top & add v0 write token.

t1/src/T1.scala

@@ -365,6 +365,8 @@ class T1(val parameter: T1Parameter)
   val decode: Instance[VectorDecoder] = Instantiate(new VectorDecoder(parameter.decoderParam))
   omInstance.decoderIn := Property(decode.om.asAnyClassType)
 
+  val tokenManager: Instance[T1TokenManager] = Instantiate(new T1TokenManager(parameter))
+
   // TODO: cover overflow
   // TODO: uarch doc about the order of instructions
   val instructionCounter:     UInt = RegInit(0.U(parameter.instructionIndexBits.W))
@@ -629,6 +631,8 @@ class T1(val parameter: T1Parameter)
       */
     val laneAndLSUFinish: Bool = control.endTag.asUInt.andR
 
+    val v0WriteFinish = !ohCheck(tokenManager.v0WriteValid, control.record.instructionIndex, parameter.chainingSize)
+
     /** lsu is finished when report bits matched corresponding slot
       * lsu send `lastReport` to [[T1]], this check if the report contains this slot.
       * this signal is used to update the `control.endTag`.
@@ -657,7 +661,7 @@ class T1(val parameter: T1Parameter)
     }
       // state machine starts here
       .otherwise {
-        when(laneAndLSUFinish) {
+        when(laneAndLSUFinish && v0WriteFinish) {
           control.state.wLast := true.B
         }
 
@@ -1585,6 +1589,12 @@ class T1(val parameter: T1Parameter)
       completedVec(index) := lane.laneResponse.bits.ffoSuccess
       flotReduceValid(index).foreach(d => d := lane.laneResponse.bits.fpReduceValid.get)
     }
+
+    // token manager
+    tokenManager.writeV0(index).valid := lane.vrfWriteChannel.fire && (lane.vrfWriteChannel.bits.vd === 0.U)
+    tokenManager.writeV0(index).bits := lane.vrfWriteChannel.bits.instructionIndex
+    tokenManager.instructionFinish(index) := lane.instructionFinished
+
     lane
   }
 

t1/src/sequencer/T1TokenManager.scala

@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileCopyrightText: 2022 Jiuyang Liu <[email protected]>
+
+package org.chipsalliance.t1.rtl
+
+import chisel3._
+import chisel3.experimental.hierarchy.{instantiable, public}
+import chisel3.util._
+
+@instantiable
+class T1TokenManager(parameter: T1Parameter) extends Module {
+  @public
+  val writeV0 = IO(Vec(parameter.laneNumber, Flipped(Valid(UInt(parameter.instructionIndexBits.W)))))
+
+  @public
+  val instructionFinish: Vec[UInt] = IO(Vec(parameter.laneNumber, Input(UInt(parameter.chainingSize.W))))
+
+  @public
+  val v0WriteValid = IO(Output(UInt(parameter.chainingSize.W)))
+
+  // v0 write token
+  val v0WriteValidVec: Seq[UInt] = Seq.tabulate(parameter.laneNumber) { laneIndex =>
+    val update: ValidIO[UInt] = writeV0(laneIndex)
+    val clear: UInt = instructionFinish(laneIndex)
+    val updateOH = maskAnd(update.valid, indexToOH(update.bits, parameter.chainingSize)).asUInt
+    VecInit(Seq.tabulate(parameter.chainingSize) { chainingIndex =>
+      val res = RegInit(false.B)
+      when(updateOH(chainingIndex) || clear(chainingIndex)) {
+        res := updateOH(chainingIndex)
+      }
+      res
+    }).asUInt
+  }
+
+  v0WriteValid := v0WriteValidVec.reduce(_ | _)
+}