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[t1emu] add coverage for different overlap type with lsu
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@Clo91eaf
Clo91eaf committed Nov 14, 2024
1 parent cf74fc1 commit 973ac0c
Showing 1 changed file with 136 additions and 94 deletions.
230 changes: 136 additions & 94 deletions t1/src/T1.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -24,6 +24,7 @@ import chisel3.util.{
Mux1H,
OHToUInt,
Pipe,
PriorityEncoder,
RegEnable,
UIntToOH,
Valid,
Expand Down Expand Up @@ -1799,106 +1800,147 @@ class T1(val parameter: T1Parameter)
probeWire.retire.valid := io.retire.rd.valid
probeWire.retire.bits := io.retire.rd.bits.rdData
probeWire.idle := slots.map(_.state.idle).reduce(_ && _)
}

// coverage
// unsupported 64-bit instructions for 32-bit xlen
val zve32f = Seq(
// format: off
"vfadd.vf", "vfadd.vv", "vfclass.v", "vfcvt.f.x.v",
"vfcvt.f.xu.v", "vfcvt.rtz.x.f.v", "vfcvt.rtz.xu.f.v", "vfcvt.x.f.v",
"vfcvt.xu.f.v", "vfdiv.vf", "vfdiv.vv", "vfmacc.vf",
"vfmacc.vv", "vfmadd.vf", "vfmadd.vv", "vfmax.vf",
"vfmax.vv", "vfmerge.vfm", "vfmin.vf", "vfmin.vv",
"vfmsac.vf", "vfmsac.vv", "vfmsub.vf", "vfmsub.vv",
"vfmul.vf", "vfmul.vv", "vfmv.f.s", "vfmv.s.f",
"vfmv.v.f", "vfnmacc.vf", "vfnmacc.vv", "vfnmadd.vf",
"vfnmadd.vv", "vfnmsac.vf", "vfnmsac.vv", "vfnmsub.vf",
"vfnmsub.vv", "vfrdiv.vf", "vfrec7.v", "vfredmax.vs",
"vfredmin.vs", "vfredosum.vs", "vfredusum.vs", "vfrsqrt7.v",
"vfrsub.vf", "vfsgnj.vf", "vfsgnj.vv", "vfsgnjn.vf",
"vfsgnjn.vv", "vfsgnjx.vf", "vfsgnjx.vv", "vfsqrt.v",
"vfsub.vf", "vfsub.vv", "vmfeq.vf", "vmfeq.vv",
"vmfge.vf", "vmfgt.vf", "vmfle.vf", "vmfle.vv",
"vmflt.vf", "vmflt.vv", "vmfne.vf", "vmfne.vv"
// format: on
)
val zve64f = Seq(
// format: off
"vfncvt.f.f.w", "vfncvt.f.x.w", "vfncvt.f.xu.w", "vfncvt.rod.f.f.w", "vfncvt.rtz.x.f.w", "vfncvt.rtz.xu.f.w", "vfncvt.x.f.w", "vfncvt.xu.f.w",
"vfslide1down.vf", "vfslide1up.vf",
"vfwadd.vf", "vfwadd.vv", "vfwadd.wf", "vfwadd.wv",
"vfwcvt.f.f.v", "vfwcvt.f.x.v", "vfwcvt.f.xu.v", "vfwcvt.rtz.x.f.v", "vfwcvt.rtz.xu.f.v", "vfwcvt.x.f.v", "vfwcvt.xu.f.v",
"vfwmacc.vf", "vfwmacc.vv", "vfwmsac.vf", "vfwmsac.vv",
"vfwmul.vf", "vfwmul.vv", "vfwnmacc.vf", "vfwnmacc.vv",
"vfwnmsac.vf", "vfwnmsac.vv", "vfwredosum.vs", "vfwredusum.vs",
"vfwsub.vf", "vfwsub.vv", "vfwsub.wf", "vfwsub.wv",
// format: on
)
val zve64x = Seq(
// format: off
"vl1re64.v", "vl2re64.v", "vl4re64.v", "vl8re64.v",
"vle64.v", "vle64ff.v", "vloxei64.v", "vlse64.v", "vluxei64.v",
"vse64.v", "vsoxei64.v", "vsse64.v", "vsuxei64.v",
"vsext.vf8", "vzext.vf8"
// format: on
)
val instructions: Seq[Instruction] = parameter.decoderParam.allInstructions.filter { instruction: Instruction =>
// format: off
!(zve64x.contains(instruction.name) && parameter.xLen == 32) &&
!(zve64f.contains(instruction.name) && parameter.xLen == 32 && parameter.fpuEnable) &&
!((zve32f ++ zve64f).contains(instruction.name) && !parameter.fpuEnable)
// format: on
}

// coverage for one instruction
instructions.map { instruction: Instruction =>
val coverMatch =
Sequence.BoolSequence(
requestReg.valid && requestReg.bits.issue.instruction === BitPat("b" + instruction.encoding.toString)
)
CoverProperty(coverMatch, label = Some(s"t1_cover_1_${instruction.name}"))
}
// coverage
// unsupported 64-bit instructions for 32-bit xlen
val zve32f = Seq(
// format: off
"vfadd.vf", "vfadd.vv", "vfclass.v", "vfcvt.f.x.v",
"vfcvt.f.xu.v", "vfcvt.rtz.x.f.v", "vfcvt.rtz.xu.f.v", "vfcvt.x.f.v",
"vfcvt.xu.f.v", "vfdiv.vf", "vfdiv.vv", "vfmacc.vf",
"vfmacc.vv", "vfmadd.vf", "vfmadd.vv", "vfmax.vf",
"vfmax.vv", "vfmerge.vfm", "vfmin.vf", "vfmin.vv",
"vfmsac.vf", "vfmsac.vv", "vfmsub.vf", "vfmsub.vv",
"vfmul.vf", "vfmul.vv", "vfmv.f.s", "vfmv.s.f",
"vfmv.v.f", "vfnmacc.vf", "vfnmacc.vv", "vfnmadd.vf",
"vfnmadd.vv", "vfnmsac.vf", "vfnmsac.vv", "vfnmsub.vf",
"vfnmsub.vv", "vfrdiv.vf", "vfrec7.v", "vfredmax.vs",
"vfredmin.vs", "vfredosum.vs", "vfredusum.vs", "vfrsqrt7.v",
"vfrsub.vf", "vfsgnj.vf", "vfsgnj.vv", "vfsgnjn.vf",
"vfsgnjn.vv", "vfsgnjx.vf", "vfsgnjx.vv", "vfsqrt.v",
"vfsub.vf", "vfsub.vv", "vmfeq.vf", "vmfeq.vv",
"vmfge.vf", "vmfgt.vf", "vmfle.vf", "vmfle.vv",
"vmflt.vf", "vmflt.vv", "vmfne.vf", "vmfne.vv"
// format: on
)
val zve64f = Seq(
// format: off
"vfncvt.f.f.w", "vfncvt.f.x.w", "vfncvt.f.xu.w", "vfncvt.rod.f.f.w", "vfncvt.rtz.x.f.w", "vfncvt.rtz.xu.f.w", "vfncvt.x.f.w", "vfncvt.xu.f.w",
"vfslide1down.vf", "vfslide1up.vf",
"vfwadd.vf", "vfwadd.vv", "vfwadd.wf", "vfwadd.wv",
"vfwcvt.f.f.v", "vfwcvt.f.x.v", "vfwcvt.f.xu.v", "vfwcvt.rtz.x.f.v", "vfwcvt.rtz.xu.f.v", "vfwcvt.x.f.v", "vfwcvt.xu.f.v",
"vfwmacc.vf", "vfwmacc.vv", "vfwmsac.vf", "vfwmsac.vv",
"vfwmul.vf", "vfwmul.vv", "vfwnmacc.vf", "vfwnmacc.vv",
"vfwnmsac.vf", "vfwnmsac.vv", "vfwredosum.vs", "vfwredusum.vs",
"vfwsub.vf", "vfwsub.vv", "vfwsub.wf", "vfwsub.wv",
// format: on
)
val zve64x = Seq(
// format: off
"vl1re64.v", "vl2re64.v", "vl4re64.v", "vl8re64.v",
"vle64.v", "vle64ff.v", "vloxei64.v", "vlse64.v", "vluxei64.v",
"vse64.v", "vsoxei64.v", "vsse64.v", "vsuxei64.v",
"vsext.vf8", "vzext.vf8"
// format: on
)
val instructions: Seq[Instruction] = parameter.decoderParam.allInstructions.filter { instruction: Instruction =>
// format: off
!(zve64x.contains(instruction.name) && parameter.xLen == 32) &&
!(zve64f.contains(instruction.name) && parameter.xLen == 32 && parameter.fpuEnable) &&
!((zve32f ++ zve64f).contains(instruction.name) && !parameter.fpuEnable)
// format: on
}

// coverage for two instructions
instructions.map { case instructionNew: Instruction =>
instructions.map { case instructionOld: Instruction =>
val issueInstructionOld = RegEnable(requestReg.bits.issue.instruction, requestReg.valid)
val coverMatchNew = Sequence.BoolSequence(
requestReg.valid && requestReg.bits.issue.instruction === BitPat("b" + instructionNew.encoding.toString)
)
val coverMatchOld =
Sequence.BoolSequence(issueInstructionOld === BitPat("b" + instructionOld.encoding.toString))
CoverProperty(
coverMatchNew.and(coverMatchOld),
label = Some(s"t1_cover_2_${instructionOld.name}_with_${instructionNew.name}")
)
// coverage for one instruction
instructions.map { instruction: Instruction =>
val coverMatch =
Sequence.BoolSequence(
requestReg.valid && requestReg.bits.issue.instruction === BitPat("b" + instruction.encoding.toString)
)
CoverProperty(coverMatch, label = Some(s"1_${instruction.name}"))
}
}

// coverage for different sew / vlmul / vl
val vsews: Seq[Int] = Seq(0, 1, 2)
val sews: Seq[Int] = Seq(8, 16, 32)
val vlmuls: Seq[Int] = Seq(0, 1, 2, 3, 6, 7)
val lmuls: Seq[Double] = Seq(1, 2, 4, 8, -1, -1, 0.25, 0.5)
val vls: Seq[(Double, Int)] =
Seq((1.0, 0), (1.0, -1), (0.25, -1), (0.25, 0), (0.25, 1), (0.5, -1), (0.5, 0), (0.5, 1))
vsews.map { vsew =>
vlmuls.map { vlmul =>
vls.map { case (vla, vlb) =>
val sew = sews(vsew)
val lmul = lmuls(vlmul)
val vlmax = parameter.vLen * lmul / sew
val vl = (vlmax * vla).toInt + vlb

val coverMatch = Sequence.BoolSequence(
requestReg.valid && requestReg.bits.issue.vl === vl.U &&
T1Issue.vlmul(requestReg.bits.issue) === vlmul.U &&
T1Issue.vsew(requestReg.bits.issue) === vsew.U
// coverage for two instructions
instructions.map { case instructionNew: Instruction =>
instructions.map { case instructionOld: Instruction =>
val issueInstructionOld = RegEnable(requestReg.bits.issue.instruction, requestReg.valid)
val coverMatchNew = Sequence.BoolSequence(
requestReg.valid && requestReg.bits.issue.instruction === BitPat("b" + instructionNew.encoding.toString)
)
val coverMatchOld =
Sequence.BoolSequence(issueInstructionOld === BitPat("b" + instructionOld.encoding.toString))
CoverProperty(
coverMatchNew.and(coverMatchOld),
label = Some(s"2_${instructionOld.name}_and_${instructionNew.name}")
)
}
}

// coverage for different sew / vlmul / vl
val vsews: Seq[Int] = Seq(0, 1, 2)
val sews: Seq[Int] = Seq(8, 16, 32)
val vlmuls: Seq[Int] = Seq(0, 1, 2, 3, 6, 7)
val lmuls: Seq[Double] = Seq(1, 2, 4, 8, -1, -1, 0.25, 0.5)
val vls: Seq[(Double, Int)] =
Seq((1.0, 0), (1.0, -1), (0.25, -1), (0.25, 0), (0.25, 1), (0.5, -1), (0.5, 0), (0.5, 1))
vsews.map { vsew =>
vlmuls.map { vlmul =>
vls.map { case (vla, vlb) =>
val sew = sews(vsew)
val lmul = lmuls(vlmul)
val vlmax = parameter.vLen * lmul / sew
val vl = (vlmax * vla).toInt + vlb

val coverMatch = Sequence.BoolSequence(
requestReg.valid && requestReg.bits.issue.vl === vl.U &&
T1Issue.vlmul(requestReg.bits.issue) === vlmul.U &&
T1Issue.vsew(requestReg.bits.issue) === vsew.U
)

CoverProperty(coverMatch, label = Some(s"t1_cover_3_sew_${sew}_lmul_${lmul}_vl_${vl}"))
CoverProperty(coverMatch, label = Some(s"3_sew_${sew}_lmul_${lmul}_vl_${vl}"))
}
}
}
}

// coverage for lsu (load / store / other) with slots (contain / intersection / disjoint)

// TODO:load unit probe

// store unit probe
val storeUnitProbe = probeWire.lsuProbe.storeUnitProbe

val storeRangeStartNew = storeUnitProbe.address
val storeRangeEndNew = storeUnitProbe.address + PriorityEncoder(storeUnitProbe.mask)
val storeRangeStartOld = RegEnable(storeUnitProbe.address, storeUnitProbe.valid)
val storeRangeEndOld =
RegEnable(storeUnitProbe.address + PriorityEncoder(storeUnitProbe.mask), storeUnitProbe.valid)

val storeContain = storeRangeStartOld <= storeRangeStartNew && storeRangeEndNew <= storeRangeEndOld ||
storeRangeStartNew <= storeRangeStartOld && storeRangeEndOld <= storeRangeEndNew
val storeIntersection = storeRangeStartNew <= storeRangeStartOld && storeRangeEndNew <= storeRangeEndOld ||
storeRangeStartOld <= storeRangeStartNew && storeRangeEndOld <= storeRangeEndNew
val storeDisjoint = storeRangeEndNew <= storeRangeStartOld || storeRangeEndOld <= storeRangeEndNew

CoverProperty(storeUnitProbe.valid && storeContain, label = Some("4_store_contain"))
CoverProperty(storeUnitProbe.valid && storeIntersection, label = Some("4_store_intersection"))
CoverProperty(storeUnitProbe.valid && storeDisjoint, label = Some("4_store_disjoint"))

// other unit probe
val otherUnitProbe = probeWire.lsuProbe.otherUnitProbe

val otherRangeStartNew = otherUnitProbe.address
val otherRangeEndNew = otherUnitProbe.address + PriorityEncoder(otherUnitProbe.mask)
val otherRangeStartOld = RegEnable(otherUnitProbe.address, otherUnitProbe.valid)
val otherRangeEndOld =
RegEnable(otherUnitProbe.address + PriorityEncoder(otherUnitProbe.mask), otherUnitProbe.valid)

val otherContain = otherRangeStartOld <= otherRangeStartNew && otherRangeEndNew <= otherRangeEndOld ||
otherRangeStartNew <= otherRangeStartOld && otherRangeEndOld <= otherRangeEndNew
val otherIntersection = otherRangeStartNew <= otherRangeStartOld && otherRangeEndNew <= otherRangeEndOld ||
otherRangeStartOld <= otherRangeStartNew && otherRangeEndOld <= otherRangeEndNew

CoverProperty(otherUnitProbe.valid && otherContain, label = Some("4_other_contain"))
CoverProperty(otherUnitProbe.valid && otherIntersection, label = Some("4_other_intersection"))
CoverProperty(otherUnitProbe.valid && otherDisjoint, label = Some("4_other_disjoint"))
} // end of verification layer
}

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