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Unify functions naming in yosys_mod and remove unnecessary calls to y…
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…osys functions (#2503)

This PR ensures that all functions in `yosys_mod.cc` are prefixed with
`synlig_`.
It also makes sure that code from `yosys_mod` calls functions (if
available) from `yosys_mod`, not directly from yosys.
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@tgorochowik
tgorochowik authored Aug 5, 2024
2 parents ffbce4e + 912f1b7 commit 8a712dd
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Showing 5 changed files with 209 additions and 215 deletions.
32 changes: 16 additions & 16 deletions frontends/systemverilog/uhdm_ast.cc
View file
Original file line number Diff line number Diff line change
Expand Up @@ -357,21 +357,21 @@ static std::pair<size_t, size_t> set_multirange_dimensions(AST::AstNode *wire_no
if (ranges[i]->children.size() == 1) {
ranges[i]->children.push_back(ranges[i]->children[0]->clone());
}
while (simplify(ranges[i], true, false, false, 1, -1, false, false)) {
while (synlig_simplify(ranges[i], true, false, false, 1, -1, false, false)) {
}
// this workaround case, where yosys doesn't follow id2ast and simplifies it to resolve constant
if (ranges[i]->children[0]->id2ast) {
simplify_sv(ranges[i]->children[0]->id2ast, ranges[i]->children[0]);
while (simplify(ranges[i]->children[0]->id2ast, true, false, false, 1, -1, false, false)) {
while (synlig_simplify(ranges[i]->children[0]->id2ast, true, false, false, 1, -1, false, false)) {
}
}
if (ranges[i]->children[1]->id2ast) {
simplify_sv(ranges[i]->children[1]->id2ast, ranges[i]->children[1]);
while (simplify(ranges[i]->children[1]->id2ast, true, false, false, 1, -1, false, false)) {
while (synlig_simplify(ranges[i]->children[1]->id2ast, true, false, false, 1, -1, false, false)) {
}
}
simplify_sv(ranges[i], wire_node);
while (simplify(ranges[i], true, false, false, 1, -1, false, false)) {
while (synlig_simplify(ranges[i], true, false, false, 1, -1, false, false)) {
}
log_assert(ranges[i]->children[0]->type == AST::AST_CONSTANT);
log_assert(ranges[i]->children[1]->type == AST::AST_CONSTANT);
Expand Down Expand Up @@ -551,7 +551,7 @@ static void resolve_wiretype(AST::AstNode *wire_node)
// we need to setup current top ast as this simplify
// needs to have access to all already defined ids
simplify_sv(wiretype_ast, nullptr);
while (simplify(wire_node, true, false, false, 1, -1, false, false)) {
while (synlig_simplify(wire_node, true, false, false, 1, -1, false, false)) {
}
log_assert(!wiretype_ast->children.empty());
if ((wiretype_ast->children[0]->type == AST::AST_STRUCT || wiretype_ast->children[0]->type == AST::AST_UNION) &&
Expand Down Expand Up @@ -1134,7 +1134,7 @@ static int simplify_struct(AST::AstNode *snode, int base_offset, AST::AstNode *p
int packed_width = -1;
for (auto s : snode->children) {
if (s->type == AST::AST_RANGE) {
while (simplify(s, true, false, false, 1, -1, false, false)) {
while (synlig_simplify(s, true, false, false, 1, -1, false, false)) {
};
}
}
Expand Down Expand Up @@ -1450,7 +1450,7 @@ static void simplify_sv(AST::AstNode *current_node, AST::AstNode *parent_node)
current_node->attributes[UhdmAst::is_simplified_wire()] = AST::AstNode::mkconst_int(1, true);
AST_INTERNAL::current_scope[current_node->str] = current_node;
convert_packed_unpacked_range(current_node);
while (simplify(current_node, true, false, false, 1, -1, false, false)) {
while (synlig_simplify(current_node, true, false, false, 1, -1, false, false)) {
};
}
break;
Expand All @@ -1473,9 +1473,9 @@ static void simplify_sv(AST::AstNode *current_node, AST::AstNode *parent_node)
current_node->children[0] = nullptr;
current_node->children[1] = nullptr;
delete_children(current_node);
while (simplify(low_high_bound->children[0], true, false, false, 1, -1, false, false)) {
while (synlig_simplify(low_high_bound->children[0], true, false, false, 1, -1, false, false)) {
};
while (simplify(low_high_bound->children[1], true, false, false, 1, -1, false, false)) {
while (synlig_simplify(low_high_bound->children[1], true, false, false, 1, -1, false, false)) {
};
log_assert(low_high_bound->children[0]->type == AST::AST_CONSTANT);
log_assert(low_high_bound->children[1]->type == AST::AST_CONSTANT);
Expand Down Expand Up @@ -1732,7 +1732,7 @@ AST::AstNode *UhdmAst::process_value(vpiHandle obj_h)
}
// handle vpiBinStrVal, vpiDecStrVal and vpiHexStrVal
if (val_str.find('\'') != std::string::npos) {
return ::systemverilog_plugin::const2ast(std::move(val_str), caseType, false);
return ::systemverilog_plugin::synlig_const2ast(std::move(val_str), caseType, false);
} else {
auto size = vpi_get(vpiSize, obj_h);
std::string size_str;
Expand All @@ -1748,7 +1748,7 @@ AST::AstNode *UhdmAst::process_value(vpiHandle obj_h)
size_str = "1";
}
}
auto c = ::systemverilog_plugin::const2ast(size_str + strValType + val_str, caseType, false);
auto c = ::systemverilog_plugin::synlig_const2ast(size_str + strValType + val_str, caseType, false);
if (size <= 0) {
// unsized unbased const
c->is_unsized = true;
Expand Down Expand Up @@ -2289,26 +2289,26 @@ void UhdmAst::simplify_parameter(AST::AstNode *parameter, AST::AstNode *module_n
// second child should be parameter range (optional)
log_assert(!parameter->children.empty());
simplify_sv(parameter->children[0], parameter);
while (simplify(parameter->children[0], true, false, false, 1, -1, false, false)) {
while (synlig_simplify(parameter->children[0], true, false, false, 1, -1, false, false)) {
}
// follow id2ast as yosys doesn't do it by default
if (parameter->children[0]->id2ast) {
simplify_sv(parameter->children[0]->id2ast, parameter);
while (simplify(parameter->children[0]->id2ast, true, false, false, 1, -1, false, false)) {
while (synlig_simplify(parameter->children[0]->id2ast, true, false, false, 1, -1, false, false)) {
}
}
if (parameter->children.size() > 1) {
simplify_sv(parameter->children[1], parameter);
while (simplify(parameter->children[1], true, false, false, 1, -1, false, false)) {
while (synlig_simplify(parameter->children[1], true, false, false, 1, -1, false, false)) {
}
if (parameter->children[1]->id2ast) {
simplify_sv(parameter->children[1]->id2ast, parameter);
while (simplify(parameter->children[1]->id2ast, true, false, false, 1, -1, false, false)) {
while (synlig_simplify(parameter->children[1]->id2ast, true, false, false, 1, -1, false, false)) {
}
}
}
// then simplify parameter to AST_CONSTANT or AST_REALVALUE
while (simplify(parameter, true, false, false, 1, -1, false, false)) {
while (synlig_simplify(parameter, true, false, false, 1, -1, false, false)) {
}
clear_current_scope();
}
Expand Down
26 changes: 13 additions & 13 deletions third_party/yosys_mod/synlig_const2ast.cc
View file
Original file line number Diff line number Diff line change
Expand Up @@ -50,7 +50,7 @@ using namespace Yosys;
using namespace Yosys::AST;

// divide an arbitrary length decimal number by two and return the rest
static int my_decimal_div_by_two(std::vector<uint8_t> &digits)
static int synlig_decimal_div_by_two(std::vector<uint8_t> &digits)
{
int carry = 0;
for (size_t i = 0; i < digits.size(); i++) {
Expand All @@ -66,7 +66,7 @@ static int my_decimal_div_by_two(std::vector<uint8_t> &digits)
}

// find the number of significant bits in a binary number (not including the sign bit)
static int my_ilog2(int x)
static int synlig_ilog2(int x)
{
int ret = 0;
while (x != 0 && x != -1) {
Expand All @@ -77,7 +77,7 @@ static int my_ilog2(int x)
}

// parse a binary, decimal, hexadecimal or octal number with support for special bits ('x', 'z' and '?')
static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int len_in_bits, int base, char case_type, bool is_unsized)
static void synlig_strtobin(std::vector<RTLIL::State> &data, const char *str, int len_in_bits, int base, char case_type, bool is_unsized)
{
// all digits in string (MSB at index 0)
std::vector<uint8_t> digits;
Expand All @@ -103,9 +103,9 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le

if (base == 10) {
while (!digits.empty())
data.push_back(my_decimal_div_by_two(digits) ? State::S1 : State::S0);
data.push_back(synlig_decimal_div_by_two(digits) ? State::S1 : State::S0);
} else {
int bits_per_digit = my_ilog2(base - 1);
int bits_per_digit = synlig_ilog2(base - 1);
for (auto it = digits.rbegin(), e = digits.rend(); it != e; it++) {
if (*it > (base - 1) && *it < 0xf0)
log_file_error(current_filename, get_line_num(), "Digit larger than %d used in in base-%d constant.\n", base - 1, base);
Expand Down Expand Up @@ -153,10 +153,10 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le
}

// convert the Verilog code for a constant to an AST node
AstNode *systemverilog_plugin::const2ast(std::string code, char case_type, bool warn_z)
AstNode *systemverilog_plugin::synlig_const2ast(std::string code, char case_type, bool warn_z)
{
if (warn_z) {
AstNode *ret = const2ast(code, case_type);
AstNode *ret = synlig_const2ast(code, case_type);
if (ret != nullptr && std::find(ret->bits.begin(), ret->bits.end(), RTLIL::State::Sz) != ret->bits.end())
log_warning("Yosys has only limited support for tri-state logic at the moment. (%s:%d)\n", current_filename.c_str(), get_line_num());
return ret;
Expand Down Expand Up @@ -192,7 +192,7 @@ AstNode *systemverilog_plugin::const2ast(std::string code, char case_type, bool
// Simple base-10 integer
if (*endptr == 0) {
std::vector<RTLIL::State> data;
my_strtobin(data, str, -1, 10, case_type, false);
synlig_strtobin(data, str, -1, 10, case_type, false);
if (data.back() == State::S1)
data.push_back(State::S0);
return AstNode::mkconst_bits(data, true);
Expand All @@ -214,25 +214,25 @@ AstNode *systemverilog_plugin::const2ast(std::string code, char case_type, bool
switch (*(endptr + 1)) {
case 'b':
case 'B':
my_strtobin(data, endptr + 2, len_in_bits, 2, case_type, is_unsized);
synlig_strtobin(data, endptr + 2, len_in_bits, 2, case_type, is_unsized);
break;
case 'o':
case 'O':
my_strtobin(data, endptr + 2, len_in_bits, 8, case_type, is_unsized);
synlig_strtobin(data, endptr + 2, len_in_bits, 8, case_type, is_unsized);
break;
case 'd':
case 'D':
my_strtobin(data, endptr + 2, len_in_bits, 10, case_type, is_unsized);
synlig_strtobin(data, endptr + 2, len_in_bits, 10, case_type, is_unsized);
break;
case 'h':
case 'H':
my_strtobin(data, endptr + 2, len_in_bits, 16, case_type, is_unsized);
synlig_strtobin(data, endptr + 2, len_in_bits, 16, case_type, is_unsized);
break;
default:
char next_char = char(tolower(*(endptr + 1)));
if (next_char == '0' || next_char == '1' || next_char == 'x' || next_char == 'z') {
is_unsized = true;
my_strtobin(data, endptr + 1, 1, 2, case_type, is_unsized);
synlig_strtobin(data, endptr + 1, 1, 2, case_type, is_unsized);
} else {
return NULL;
}
Expand Down
2 changes: 1 addition & 1 deletion third_party/yosys_mod/synlig_const2ast.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@
namespace systemverilog_plugin
{
// this function converts a Verilog constant to an AST_CONSTANT node
Yosys::AST::AstNode *const2ast(std::string code, char case_type = 0, bool warn_z = false);
Yosys::AST::AstNode *synlig_const2ast(std::string code, char case_type = 0, bool warn_z = false);
} // namespace systemverilog_plugin

#endif // SYSTEMVERILOG_PLUGIN_CONST2AST_H
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