User mode support #187

mkurc-ant · 2024-06-12T08:04:09Z

This PR adds User mode support to VeeR EL2 core. This implies also:

enabling U bit in misa
adding new fields to mstatus CSR
adding CSR access control
adding new exception code for ECALL.U instruction.
preventing privilege instructions from running in user mode
adding user mode accessible shadow CSRs for performance counters
adding mcounteren CSR that controls access to counter shadow CSRs
updating PMP behavior to account for user mode

Along with user mode support there's also extended PMP (Smepmp) support added.

Both user mode and Smepmp are disabled by default. They need to be enabled via veer.config script. To enable user mode append:

-set=user_mode=1

to its invocation. And to enable Smepmp append:

-set=smepmp=1

With the PR there are new tests added that exercise new features.

github-actions

Remaining comments which cannot be posted as a review comment to avoid GitHub Rate Limit

verible-verilog-format

design/el2_pmp.sv|156|
design/el2_pmp.sv|159|
design/el2_pmp.sv|305|
design/el2_veer.sv|885|
design/el2_veer.sv|889|
design/el2_veer.sv|893|
design/include/el2_def.sv|440|
design/include/el2_def.sv|442|

github-actions · 2024-06-12T08:05:00Z

design/dec/el2_dec_decode_ctl.sv

   assign dec_csr_rdaddr_d[11:0] =  {12{dec_csr_any_unq_d}} & i0[31:20];
-   assign dec_csr_wraddr_r[11:0] =  {12{r_d.csrwen & r_d.i0valid}} & r_d.csrwaddr[11:0];
+   assign dec_csr_rdaddr_r[11:0] =  {12{~r_d.csrwen & r_d.i0valid}} & r_d.csraddr[11:0];
+   assign dec_csr_wraddr_r[11:0] =  {12{ r_d.csrwen & r_d.i0valid}} & r_d.csraddr[11:0];


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign dec_csr_rdaddr_d[11:0] = {12{dec_csr_any_unq_d}} & i0[31:20];

assign dec_csr_wraddr_r[11:0] = {12{r_d.csrwen & r_d.i0valid}} & r_d.csrwaddr[11:0];

assign dec_csr_rdaddr_r[11:0] = {12{~r_d.csrwen & r_d.i0valid}} & r_d.csraddr[11:0];

assign dec_csr_wraddr_r[11:0] = {12{ r_d.csrwen & r_d.i0valid}} & r_d.csraddr[11:0];

assign dec_csr_rdaddr_d[11:0] = {12{dec_csr_any_unq_d}} & i0[31:20];

assign dec_csr_rdaddr_r[11:0] = {12{~r_d.csrwen & r_d.i0valid}} & r_d.csraddr[11:0];

assign dec_csr_wraddr_r[11:0] = {12{r_d.csrwen & r_d.i0valid}} & r_d.csraddr[11:0];

github-actions · 2024-06-12T08:05:01Z

design/dec/el2_dec_decode_ctl.sv

   // If we are writing MIE or MSTATUS, hold off the external interrupt for a cycle on the write.
-   assign dec_csr_stall_int_ff = ((r_d.csrwaddr[11:0] == 12'h300) | (r_d.csrwaddr[11:0] == 12'h304)) & r_d.csrwen & r_d.i0valid & ~dec_tlu_i0_kill_writeb_wb;
+   assign dec_csr_stall_int_ff = ((r_d.csraddr[11:0] == 12'h300) | (r_d.csraddr[11:0] == 12'h304)) & r_d.csrwen & r_d.i0valid & ~dec_tlu_i0_kill_writeb_wb;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// If we are writing MIE or MSTATUS, hold off the external interrupt for a cycle on the write.

assign dec_csr_stall_int_ff = ((r_d.csrwaddr[11:0] == 12'h300) | (r_d.csrwaddr[11:0] == 12'h304)) & r_d.csrwen & r_d.i0valid & ~dec_tlu_i0_kill_writeb_wb;

assign dec_csr_stall_int_ff = ((r_d.csraddr[11:0] == 12'h300) | (r_d.csraddr[11:0] == 12'h304)) & r_d.csrwen & r_d.i0valid & ~dec_tlu_i0_kill_writeb_wb;

// If we are writing MIE or MSTATUS, hold off the external interrupt for a cycle on the write.

assign dec_csr_stall_int_ff = ((r_d.csraddr[11:0] == 12'h300) | (r_d.csraddr[11:0] == 12'h304)) & r_d.csrwen & r_d.i0valid & ~dec_tlu_i0_kill_writeb_wb;

github-actions · 2024-06-12T08:05:01Z

design/dec/el2_dec_decode_ctl.sv

   assign d_d.csrwen                =  dec_csr_wen_unq_d   & i0_legal_decode_d;
   assign d_d.csrwonly              =  i0_csr_write_only_d & dec_i0_decode_d;
-   assign d_d.csrwaddr[11:0]        =  (d_d.csrwen) ? i0[31:20] : '0;    // csr write address for rd==0 case
+   assign d_d.csraddr[11:0]         =  i0[31:20]; // csr read/write address


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign d_d.csrwen = dec_csr_wen_unq_d & i0_legal_decode_d;

assign d_d.csrwonly = i0_csr_write_only_d & dec_i0_decode_d;

assign d_d.csrwaddr[11:0] = (d_d.csrwen) ? i0[31:20] : '0; // csr write address for rd==0 case

assign d_d.csraddr[11:0] = i0[31:20]; // csr read/write address

assign d_d.csrwen = dec_csr_wen_unq_d & i0_legal_decode_d;

assign d_d.csrwonly = i0_csr_write_only_d & dec_i0_decode_d;

assign d_d.csraddr[11:0] = i0[31:20]; // csr read/write address

github-actions · 2024-06-12T08:05:01Z

design/dec/el2_dec_decode_ctl.sv

@@ -1309,7 +1311,7 @@ end : cam_array

   assign d_d.csrwen                =  dec_csr_wen_unq_d   & i0_legal_decode_d;
   assign d_d.csrwonly              =  i0_csr_write_only_d & dec_i0_decode_d;
-   assign d_d.csrwaddr[11:0]        =  (d_d.csrwen) ? i0[31:20] : '0;    // csr write address for rd==0 case
+   assign d_d.csraddr[11:0]         =  i0[31:20]; // csr read/write address


   rvdff  #(3) i0cgff               (.*, .clk(active_clk),            .din(i0_pipe_en[3:1]), .dout(i0_pipe_en[2:0]));


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

rvdff #(3) i0cgff (.*, .clk(active_clk), .din(i0_pipe_en[3:1]), .dout(i0_pipe_en[2:0]));

rvdff #(3) i0cgff (

.*,

.clk (active_clk),

.din (i0_pipe_en[3:1]),

.dout(i0_pipe_en[2:0])

);

github-actions · 2024-06-12T08:05:01Z

design/dec/el2_dec_pmp_ctl.sv

@@ -23,7 +23,6 @@
 //
 //********************************************************************************

-
 module el2_dec_pmp_ctl
 import el2_pkg::*;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

import el2_pkg::*;

import el2_pkg::*;

github-actions · 2024-06-12T08:05:03Z

design/el2_pmp.sv

+             (pmp_req_type == READ) |
+             (pmp_req_type == WRITE);
+        // Execute only on M/U
+        2'b10: result = (pmp_req_type == EXEC);


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

2'b10: result = (pmp_req_type == EXEC);

2'b10: result = (pmp_req_type == EXEC);

github-actions · 2024-06-12T08:05:03Z

design/el2_pmp.sv

+        2'b11: result =
+             (pmp_req_type == EXEC) |
+            ((pmp_req_type == READ) & ~priv_mode);


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

2'b11: result =

(pmp_req_type == EXEC) |

((pmp_req_type == READ) & ~priv_mode);

2'b11: result = (pmp_req_type == EXEC) | ((pmp_req_type == READ) & ~priv_mode);

github-actions · 2024-06-12T08:05:03Z

design/el2_pmp.sv

+  function automatic logic orig_perm_check(logic pmp_cfg_lock,
+                                           logic priv_mode,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

function automatic logic orig_perm_check(logic pmp_cfg_lock,

logic priv_mode,

function automatic logic orig_perm_check(logic pmp_cfg_lock, logic priv_mode,

github-actions · 2024-06-12T08:05:03Z

design/el2_pmp.sv

+  function automatic logic access_fault_check(el2_mseccfg_pkt_t          csr_pmp_mseccfg,
+                                              el2_pmp_type_pkt_t         req_type,
+                                              logic [pt.PMP_ENTRIES-1:0] match_all,
+                                              logic any_region_enabled,
+                                              logic priv_mode,
                                              logic [pt.PMP_ENTRIES-1:0] final_perm_check);


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

function automatic logic access_fault_check(el2_mseccfg_pkt_t csr_pmp_mseccfg,

el2_pmp_type_pkt_t req_type,

logic [pt.PMP_ENTRIES-1:0] match_all,

logic any_region_enabled,

logic priv_mode,

logic [pt.PMP_ENTRIES-1:0] final_perm_check);

function automatic logic access_fault_check(

el2_mseccfg_pkt_t csr_pmp_mseccfg, el2_pmp_type_pkt_t req_type,

logic [pt.PMP_ENTRIES-1:0] match_all, logic any_region_enabled, logic priv_mode,

logic [pt.PMP_ENTRIES-1:0] final_perm_check);

github-actions · 2024-06-12T08:05:03Z

design/el2_pmp.sv

                                              logic [pt.PMP_ENTRIES-1:0] final_perm_check);

-
+`ifdef RV_USER_MODE
+  `ifdef RV_SMEPMP


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

`ifdef RV_SMEPMP

`ifdef RV_SMEPMP

github-actions · 2024-06-12T08:05:05Z

design/dec/el2_dec_tlu_ctl.sv

@@ -557,6 +540,12 @@ import el2_pkg::*;


 localparam MSTATUS_MIE   = 0;
+localparam MSTATUS_MPIE  = 1;


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Explicitly define a storage type for every parameter and localparam, (MSTATUS_MPIE). [Style: constants] [explicit-parameter-storage-type]

github-actions · 2024-06-12T08:05:05Z

design/dec/el2_dec_tlu_ctl.sv

@@ -1229,6 +1352,7 @@ end
   // [31:0] : Lower Cycle count

   localparam MCYCLEL       = 12'hb00;
+   localparam CYCLEL        = 12'hc00;


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Explicitly define a storage type for every parameter and localparam, (CYCLEL). [Style: constants] [explicit-parameter-storage-type]

github-actions · 2024-06-12T08:05:05Z

design/dec/el2_dec_tlu_ctl.sv

@@ -1251,6 +1375,7 @@ end
   // Chained with mcyclel. Note: mcyclel overflow due to a mcycleh write gets ignored.

   localparam MCYCLEH       = 12'hb80;
+   localparam CYCLEH        = 12'hc80;


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Explicitly define a storage type for every parameter and localparam, (CYCLEH). [Style: constants] [explicit-parameter-storage-type]

github-actions · 2024-06-12T08:05:05Z

design/dec/el2_dec_tlu_ctl.sv

@@ -1269,6 +1394,7 @@ end
   // one instruction will be the value read by the following instruction (i.e., the increment of instret
   // caused by the first instruction retiring happens before the write of the new value)."
   localparam MINSTRETL     = 12'hb02;
+   localparam INSTRETL      = 12'hc02;


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Explicitly define a storage type for every parameter and localparam, (INSTRETL). [Style: constants] [explicit-parameter-storage-type]

github-actions · 2024-06-12T08:05:05Z

design/dec/el2_dec_tlu_ctl.sv

@@ -1295,6 +1421,7 @@ end
   // Chained with minstretl. Note: minstretl overflow due to a minstreth write gets ignored.

   localparam MINSTRETH     = 12'hb82;
+   localparam INSTRETH      = 12'hc82;


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Explicitly define a storage type for every parameter and localparam, (INSTRETH). [Style: constants] [explicit-parameter-storage-type]

github-actions · 2024-06-12T08:05:06Z

design/dec/el2_dec_pmp_ctl.sv

+   // ----------------------------------------------------------------------
+
+   logic [pt.PMP_ENTRIES-1:0] entry_lock_eff; // Effective entry lock
+   for (genvar r = 0; r < pt.PMP_ENTRIES; r++) begin : pmpcfg_lock


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
All generate block labels must start with g_ or gen_ [Style: generate-constructs] [generate-label-prefix]

github-actions · 2024-06-12T08:05:06Z

design/dec/el2_dec_pmp_ctl.sv

+      // PMPCFG fields are WARL. Mask out bits 6:5 during write. 
+      // When Smepmp is disabled R=0 and W=1 combination is illegal mask out W


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]

Suggested change

// PMPCFG fields are WARL. Mask out bits 6:5 during write.

// When Smepmp is disabled R=0 and W=1 combination is illegal mask out W

// PMPCFG fields are WARL. Mask out bits 6:5 during write. // PMPCFG fields are WARL. Mask out bits 6:5 during write.

// When Smepmp is disabled R=0 and W=1 combination is illegal mask out W

github-actions · 2024-06-12T08:05:06Z

design/el2_veer.sv

+`ifdef RV_USER_MODE
+
+   logic priv_mode;         // Operating privilege mode, 0 - machine, 1 - user
+   logic priv_mode_eff;     // Effective privilege mode, 0 - machine, 1 - user (driven in el2_dec_tlu_ctl.sv)


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 109 [Style: line-length] [line-length]

github-actions · 2024-06-12T09:04:45Z

design/el2_pmp.sv

+    // modes. Also deny unmatched for M-mode when MSECCFG.MML is set and request type is EXEC.
+    logic access_fail = csr_pmp_mseccfg.MMWP | priv_mode |
+                       (csr_pmp_mseccfg.MML && (req_type == EXEC));
+  `else


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

`else

`else

github-actions · 2024-06-12T09:04:46Z

design/el2_pmp.sv

+  `else
+    // When in user mode and at least one PMP region is enabled deny access by default.
+    logic access_fail = any_region_enabled & priv_mode;
+  `endif


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

`endif

`endif

github-actions · 2024-06-12T09:04:46Z

design/el2_pmp.sv

+        1'b0,
+        1'b0,
+`endif
+        region_perm_check[c]);


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

region_perm_check[c]);

region_perm_check[c]

);

github-actions · 2024-06-12T09:04:46Z

design/el2_veer.sv

@@ -884,6 +884,16 @@ import el2_pkg::*;

   assign core_rst_l = rst_l & (dbg_core_rst_l | scan_mode);


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign core_rst_l = rst_l & (dbg_core_rst_l | scan_mode);

assign core_rst_l = rst_l & (dbg_core_rst_l | scan_mode);

github-actions · 2024-06-12T09:04:46Z

design/el2_veer.sv

+   logic priv_mode;         // Operating privilege mode, 0 - machine, 1 - user
+   logic priv_mode_eff;     // Effective privilege mode, 0 - machine, 1 - user (driven in el2_dec_tlu_ctl.sv)
+   logic priv_mode_ns;      // Next privilege mode


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

logic priv_mode; // Operating privilege mode, 0 - machine, 1 - user

logic priv_mode_eff; // Effective privilege mode, 0 - machine, 1 - user (driven in el2_dec_tlu_ctl.sv)

logic priv_mode_ns; // Next privilege mode

logic priv_mode; // Operating privilege mode, 0 - machine, 1 - user

logic priv_mode_eff; // Effective privilege mode, 0 - machine, 1 - user (driven in el2_dec_tlu_ctl.sv)

logic priv_mode_ns; // Next privilege mode

github-actions · 2024-06-12T09:04:46Z

design/el2_veer.sv

+   logic priv_mode_eff;     // Effective privilege mode, 0 - machine, 1 - user (driven in el2_dec_tlu_ctl.sv)
+   logic priv_mode_ns;      // Next privilege mode
+
+   el2_mseccfg_pkt_t mseccfg; // mseccfg CSR for PMP


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

el2_mseccfg_pkt_t mseccfg; // mseccfg CSR for PMP

el2_mseccfg_pkt_t mseccfg; // mseccfg CSR for PMP

github-actions · 2024-06-12T09:04:46Z

design/include/el2_def.sv

+    logic MMWP;
+    logic MML;
+  } el2_mseccfg_pkt_t;
+
 //`endif


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

//`endif

//`endif

github-actions · 2024-06-12T09:04:47Z

design/include/el2_def.sv

+    logic MMWP;
+    logic MML;
+  } el2_mseccfg_pkt_t;
+
 //`endif

 endpackage // el2_pkg


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

endpackage // el2_pkg

endpackage // el2_pkg

github-actions · 2024-06-12T10:02:18Z

Links to coverage and verification reports for this PR (#187) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions · 2024-06-25T13:12:08Z

design/dec/el2_dec_tlu_ctl.sv

@@ -557,6 +540,12 @@ import el2_pkg::*;


 localparam MSTATUS_MIE   = 0;
+localparam int MSTATUS_MPIE  = 1;


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Non-type localparam names must be styled with CamelCase [Style: constants] [parameter-name-style]

We've added the int type following the fixes from Verible.
However, the case used here is consistent with other localparams in the codebase and we don't aim to reformat them in the scope on this PR.

github-actions · 2024-06-25T13:12:16Z

design/dec/el2_dec_decode_ctl.sv

@@ -920,16 +921,17 @@ end : cam_array
   assign dec_csr_any_unq_d = any_csr_d & i0_valid_d;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign dec_csr_any_unq_d = any_csr_d & i0_valid_d;

assign dec_csr_any_unq_d = any_csr_d & i0_valid_d;

The indentation level suggestions do not match the indentation of the rest of the file. Let's not apply them for now as formatting of the whole file is out of scope of this PR.

github-actions · 2024-06-25T13:12:16Z

design/dec/el2_dec_decode_ctl.sv

+   assign dec_csr_rdaddr_d[11:0] = {12{dec_csr_any_unq_d}} & i0[31:20];
+   assign dec_csr_rdaddr_r[11:0] = {12{~r_d.csrwen & r_d.i0valid}} & r_d.csraddr[11:0];
+   assign dec_csr_wraddr_r[11:0] = {12{r_d.csrwen & r_d.i0valid}} & r_d.csraddr[11:0];


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign dec_csr_rdaddr_d[11:0] = {12{dec_csr_any_unq_d}} & i0[31:20];

assign dec_csr_rdaddr_r[11:0] = {12{~r_d.csrwen & r_d.i0valid}} & r_d.csraddr[11:0];

assign dec_csr_wraddr_r[11:0] = {12{r_d.csrwen & r_d.i0valid}} & r_d.csraddr[11:0];

assign dec_csr_rdaddr_d[11:0] = {12{dec_csr_any_unq_d}} & i0[31:20];

assign dec_csr_rdaddr_r[11:0] = {12{~r_d.csrwen & r_d.i0valid}} & r_d.csraddr[11:0];

assign dec_csr_wraddr_r[11:0] = {12{r_d.csrwen & r_d.i0valid}} & r_d.csraddr[11:0];

github-actions · 2024-06-25T13:12:16Z

design/dec/el2_dec_decode_ctl.sv

+   assign d_d.csrwen        =  dec_csr_wen_unq_d   & i0_legal_decode_d;
+   assign d_d.csrwonly      =  i0_csr_write_only_d & dec_i0_decode_d;
+   assign d_d.csraddr[11:0] =  i0[31:20]; // csr read/write address


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign d_d.csrwen = dec_csr_wen_unq_d & i0_legal_decode_d;

assign d_d.csrwonly = i0_csr_write_only_d & dec_i0_decode_d;

assign d_d.csraddr[11:0] = i0[31:20]; // csr read/write address

assign d_d.csrwen = dec_csr_wen_unq_d & i0_legal_decode_d;

assign d_d.csrwonly = i0_csr_write_only_d & dec_i0_decode_d;

assign d_d.csraddr[11:0] = i0[31:20]; // csr read/write address

github-actions · 2024-06-25T13:12:16Z

design/dec/el2_dec_pmp_ctl.sv

+   output logic [31:0] dec_pmp_rddata_d,  // pmp CSR read data
+   output logic        dec_pmp_read_d,    // pmp CSR address match


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

output logic [31:0] dec_pmp_rddata_d, // pmp CSR read data

output logic dec_pmp_read_d, // pmp CSR address match

output logic [31:0] dec_pmp_rddata_d, // pmp CSR read data

output logic dec_pmp_read_d, // pmp CSR address match

github-actions · 2024-06-25T13:12:17Z

design/dec/el2_dec_pmp_ctl.sv

   output el2_pmp_cfg_pkt_t pmp_pmpcfg  [pt.PMP_ENTRIES],
   output logic [31:0]      pmp_pmpaddr [pt.PMP_ENTRIES],


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

output el2_pmp_cfg_pkt_t pmp_pmpcfg [pt.PMP_ENTRIES],

output logic [31:0] pmp_pmpaddr [pt.PMP_ENTRIES],

output el2_pmp_cfg_pkt_t pmp_pmpcfg [pt.PMP_ENTRIES],

output logic [31:0] pmp_pmpaddr[pt.PMP_ENTRIES],

github-actions · 2024-06-25T13:12:17Z

design/dec/el2_dec_pmp_ctl.sv

+   logic [pt.PMP_ENTRIES-1:0] entry_lock_eff;  // Effective entry lock
+   for (genvar r = 0; r < pt.PMP_ENTRIES; r++) begin : g_pmpcfg_lock


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

logic [pt.PMP_ENTRIES-1:0] entry_lock_eff; // Effective entry lock

for (genvar r = 0; r < pt.PMP_ENTRIES; r++) begin : g_pmpcfg_lock

logic [pt.PMP_ENTRIES-1:0] entry_lock_eff; // Effective entry lock

for (genvar r = 0; r < pt.PMP_ENTRIES; r++) begin : g_pmpcfg_lock

github-actions · 2024-06-25T13:12:17Z

design/dec/el2_dec_pmp_ctl.sv

+   // Smepmp allow modifying locked entries when mseccfg.RLB is set
+   assign entry_lock_eff[r] = pmp_pmpcfg[r].lock & ~mseccfg.RLB;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// Smepmp allow modifying locked entries when mseccfg.RLB is set

assign entry_lock_eff[r] = pmp_pmpcfg[r].lock & ~mseccfg.RLB;

// Smepmp allow modifying locked entries when mseccfg.RLB is set

assign entry_lock_eff[r] = pmp_pmpcfg[r].lock & ~mseccfg.RLB;

github-actions · 2024-06-25T13:12:17Z

design/dec/el2_dec_pmp_ctl.sv

+   // Smepmp allow modifying locked entries when mseccfg.RLB is set
+   assign entry_lock_eff[r] = pmp_pmpcfg[r].lock & ~mseccfg.RLB;
+`else
+   assign entry_lock_eff[r] = pmp_pmpcfg[r].lock;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign entry_lock_eff[r] = pmp_pmpcfg[r].lock;

assign entry_lock_eff[r] = pmp_pmpcfg[r].lock;

github-actions · 2024-06-25T13:12:17Z

design/dec/el2_dec_pmp_ctl.sv

+      // PMPCFG fields are WARL. Mask out bits 6:5 during write.
+      // When Smepmp is disabled R=0 and W=1 combination is illegal mask out W
+      // when R is cleared.
+      assign raw_wdata = dec_csr_wrdata_r[(entry_idx[1:0]*8)+7:(entry_idx[1:0]*8)+0];


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// PMPCFG fields are WARL. Mask out bits 6:5 during write.

// When Smepmp is disabled R=0 and W=1 combination is illegal mask out W

// when R is cleared.

assign raw_wdata = dec_csr_wrdata_r[(entry_idx[1:0]*8)+7:(entry_idx[1:0]*8)+0];

// PMPCFG fields are WARL. Mask out bits 6:5 during write.

// When Smepmp is disabled R=0 and W=1 combination is illegal mask out W

// when R is cleared.

assign raw_wdata = dec_csr_wrdata_r[(entry_idx[1:0]*8)+7:(entry_idx[1:0]*8)+0];

github-actions · 2024-06-25T13:12:17Z

design/el2_veer.sv

+   // Operating privilege mode, 0 - machine, 1 - user
+   logic priv_mode;
+   // Effective privilege mode, 0 - machine, 1 - user (driven in el2_dec_tlu_ctl.sv)
+   logic priv_mode_eff;
+   // Next privilege mode
+   logic priv_mode_ns;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// Operating privilege mode, 0 - machine, 1 - user

logic priv_mode;

// Effective privilege mode, 0 - machine, 1 - user (driven in el2_dec_tlu_ctl.sv)

logic priv_mode_eff;

// Next privilege mode

logic priv_mode_ns;

// Operating privilege mode, 0 - machine, 1 - user

logic priv_mode;

// Effective privilege mode, 0 - machine, 1 - user (driven in el2_dec_tlu_ctl.sv)

logic priv_mode_eff;

// Next privilege mode

logic priv_mode_ns;

github-actions · 2024-06-25T15:26:25Z

Links to coverage and verification reports for this PR (#187) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

Internal-tag: [#57661] Signed-off-by: Maciej Kurc <[email protected]>

Internal-tag: [#57674] Signed-off-by: Maciej Kurc <[email protected]>

Internal-tag: [#57788] Signed-off-by: Maciej Kurc <[email protected]>

Internal-tag: [#57785] Signed-off-by: Maciej Kurc <[email protected]>

Internal-tag: [#58029] Signed-off-by: Maciej Kurc <[email protected]>

…y sizes Internal-tag: [#58029] Signed-off-by: Maciej Kurc <[email protected]>

… fail) Internal-tag: [#58029] Signed-off-by: Maciej Kurc <[email protected]>

… checking Internal-tag: [#58029] Signed-off-by: Maciej Kurc <[email protected]>

…pening Internal-tag: [#58273] Signed-off-by: Maciej Kurc <[email protected]>

Internal-tag: [#58273] Signed-off-by: Maciej Kurc <[email protected]>

…ardware interrupts Internal-tag: [#58169] Signed-off-by: Maciej Kurc <[email protected]>

Internal-tag: [#58150] Signed-off-by: Maciej Kurc <[email protected]>

Internal-tag: [#59770] Signed-off-by: Maciej Kurc <[email protected]>

…ons. Internal-tag: [#59770] Signed-off-by: Maciej Kurc <[email protected]>

Internal-tag: [#59770] Signed-off-by: Maciej Kurc <[email protected]>

…f priv_mode Internal-tag: [#59827] Signed-off-by: Maciej Kurc <[email protected]>

…s rights) Internal-tag: [#59827] Signed-off-by: Maciej Kurc <[email protected]>

Signed-off-by: Maciej Kurc <[email protected]>

github-actions · 2024-07-03T16:47:26Z

Links to coverage and verification reports for this PR (#187) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

kgugala · 2024-07-05T09:08:08Z

LGTM

github-actions bot reviewed Jun 12, 2024

View reviewed changes

mkurc-ant force-pushed the user-mode-support-ant branch from 414f696 to 4c8dacb Compare June 25, 2024 13:11

github-actions bot reviewed Jun 25, 2024

View reviewed changes

mkurc-ant added 22 commits July 3, 2024 13:20

Set the U bit in MISA CSR

6a0c821

Internal-tag: [#57661] Signed-off-by: Maciej Kurc <[email protected]>

Add initial MISA CSR test

0d1709e

Internal-tag: [#57661] Signed-off-by: Maciej Kurc <[email protected]>

Add MPP field to mstatus CSR

9f84432

Internal-tag: [#57674] Signed-off-by: Maciej Kurc <[email protected]>

Refactored misa CSR test

84bb9bb

Internal-tag: [#57674] Signed-off-by: Maciej Kurc <[email protected]>

Add test for mstatus.MPP CSR field

ed5adb1

Internal-tag: [#57674] Signed-off-by: Maciej Kurc <[email protected]>

Add MPRV field to mstatus

2085b12

Internal-tag: [#57674] Signed-off-by: Maciej Kurc <[email protected]>

Add test for mstatus.MPRV field

3ac1299

Internal-tag: [#57674] Signed-off-by: Maciej Kurc <[email protected]>

Store mstatus.MPP as inverted so that it means M after reset

44b844d

Internal-tag: [#57674] Signed-off-by: Maciej Kurc <[email protected]>

Initial logic to store and update privilege level

43431d8

Internal-tag: [#57788] Signed-off-by: Maciej Kurc <[email protected]>

A test demonstratin M and U privilege mode switching

d062a21

Internal-tag: [#57788] Signed-off-by: Maciej Kurc <[email protected]>

Added ECALL.U mcause code

023cb71

Internal-tag: [#57788] Signed-off-by: Maciej Kurc <[email protected]>

Add mstatus CSR updates caused by events that switch privilege mode.

e4c9abc

Internal-tag: [#57788] Signed-off-by: Maciej Kurc <[email protected]>

Use constants to index mstatus signal bits

5444e25

Internal-tag: [#57788] Signed-off-by: Maciej Kurc <[email protected]>

Set mstatus.MPIE to 1 on mret

4eebf8f

Internal-tag: [#57788] Signed-off-by: Maciej Kurc <[email protected]>

Disallow privileged CSR access in user-mode

a413483

Internal-tag: [#57785] Signed-off-by: Maciej Kurc <[email protected]>

A test for CSR access from machine and user mode

2cf0fd6

Internal-tag: [#58029] Signed-off-by: Maciej Kurc <[email protected]>

Added missing CSRs to CSR access test, use statically determined arra…

b6aadf3

…y sizes Internal-tag: [#58029] Signed-off-by: Maciej Kurc <[email protected]>

Removed debug CSR reads from csr_access test as they fail (and should…

6a68791

… fail) Internal-tag: [#58029] Signed-off-by: Maciej Kurc <[email protected]>

Use privilege mode instead of effective privilege mode for CSR access…

f3ba8db

… checking Internal-tag: [#58029] Signed-off-by: Maciej Kurc <[email protected]>

Extended the CSR access test with checks if accesses are actually hap…

117520e

…pening Internal-tag: [#58273] Signed-off-by: Maciej Kurc <[email protected]>

Add logic to prevent CSR data read and write in case of access failure.

80fb3fc

Internal-tag: [#58273] Signed-off-by: Maciej Kurc <[email protected]>

Add custom commands to the testbench that allow software to trigger h…

25fa981

…ardware interrupts Internal-tag: [#58169] Signed-off-by: Maciej Kurc <[email protected]>

mkurc-ant and others added 25 commits July 3, 2024 14:32

Make PMP user mode optional according to VeeR core config

9f1b1cb

Internal-tag: [#58150] Signed-off-by: Maciej Kurc <[email protected]>

Refactored PMP test, added tests for region locking feature.

d9f97b6

Internal-tag: [#58150] Signed-off-by: Maciej Kurc <[email protected]>

Fixed typo(s)

9edeb6b

Internal-tag: [#58150] Signed-off-by: Maciej Kurc <[email protected]>

Fixed typos in PMP test

34263e1

Internal-tag: [#58150] Signed-off-by: Maciej Kurc <[email protected]>

Fix PMPCFG not being WARL, prohibit writing WR=10 combination.

2231e49

Internal-tag: [#58150] Signed-off-by: Maciej Kurc <[email protected]>

Added checking if PMPCFG is WARL in the PMP test

0935aee

Internal-tag: [#58150] Signed-off-by: Maciej Kurc <[email protected]>

Added MPRV=1 and MPP=11 test case to the PMP test

70b0ec2

Internal-tag: [#58150] Signed-off-by: Maciej Kurc <[email protected]>

Add mseccfg/mseccfgh CSRs

01827c3

Internal-tag: [#59770] Signed-off-by: Maciej Kurc <[email protected]>

Add mseccfg/mseccfgh to the CSR access checking test.

a4c449f

Internal-tag: [#59770] Signed-off-by: Maciej Kurc <[email protected]>

Made mseccfg.RLB sticky 0 if any PMP region is locked

b526eb3

Internal-tag: [#59770] Signed-off-by: Maciej Kurc <[email protected]>

Implement Smepmp behavior in RTL

87902f9

Internal-tag: [#59770] Signed-off-by: Maciej Kurc <[email protected]>

Implemented effect of mseccfg.RLB on writing PMP CSRs for locked regi…

24537cf

…ons. Internal-tag: [#59770] Signed-off-by: Maciej Kurc <[email protected]>

Use a struct for mseccfg fields

0f40dfb

Internal-tag: [#59770] Signed-off-by: Maciej Kurc <[email protected]>

Make Smepmp support configurable by veer.config

45ff089

Internal-tag: [#59770] Signed-off-by: Maciej Kurc <[email protected]>

Test for mseccfg CSR and its influence on PMP

95cedce

Internal-tag: [#59770] Signed-off-by: Maciej Kurc <[email protected]>

Enable Smepmp in the PMP test

37a1eeb

Internal-tag: [#59770] Signed-off-by: Maciej Kurc <[email protected]>

Disallow Smepmp when user mode support is disabled

546e4a5

Internal-tag: [#59770] Signed-off-by: Maciej Kurc <[email protected]>

Configure PMP to allow user-mode memory access in user-mode tests

a2e1424

Internal-tag: [#59770] Signed-off-by: Maciej Kurc <[email protected]>

Fix typos

7ed86d9

Internal-tag: [#59770] Signed-off-by: Maciej Kurc <[email protected]>

Replaced hard-coded constant with helper macros

5c731fa

Internal-tag: [#59770] Signed-off-by: Maciej Kurc <[email protected]>

Make mseccfg CSR test require Smepmp to be enabled

74e6d7c

Internal-tag: [#59770] Signed-off-by: Maciej Kurc <[email protected]>

Make PMP instruction fetch address checker use priv_mode_ns instead o…

f0d1dc0

…f priv_mode Internal-tag: [#59827] Signed-off-by: Maciej Kurc <[email protected]>

Configure PMP in mstatus CSR test (necessery as MPRV bit alters acces…

47e0fa9

…s rights) Internal-tag: [#59827] Signed-off-by: Maciej Kurc <[email protected]>

Enable VeeR User mode tests in GitHub CI

b5d70f9

Signed-off-by: Maciej Kurc <[email protected]>

apply linter fixes

e65644b

wsipak force-pushed the user-mode-support-ant branch from 4c8dacb to e65644b Compare July 3, 2024 13:27

kgugala merged commit ada3961 into main Jul 5, 2024
243 checks passed

kgugala deleted the user-mode-support-ant branch July 5, 2024 09:08

	2'b10: result = (pmp_req_type == EXEC);
	2'b10: result = (pmp_req_type == EXEC);

		function automatic logic orig_perm_check(logic pmp_cfg_lock,
		logic priv_mode,

		@@ -557,6 +540,12 @@ import el2_pkg::*;


		localparam MSTATUS_MIE = 0;
		localparam MSTATUS_MPIE = 1;

		// PMPCFG fields are WARL. Mask out bits 6:5 during write.
		// When Smepmp is disabled R=0 and W=1 combination is illegal mask out W

		@@ -884,6 +884,16 @@ import el2_pkg::*;

		assign core_rst_l = rst_l & (dbg_core_rst_l \| scan_mode);

	el2_mseccfg_pkt_t mseccfg; // mseccfg CSR for PMP
	el2_mseccfg_pkt_t mseccfg; // mseccfg CSR for PMP

		@@ -557,6 +540,12 @@ import el2_pkg::*;


		localparam MSTATUS_MIE = 0;
		localparam int MSTATUS_MPIE = 1;

		@@ -920,16 +921,17 @@ end : cam_array
		assign dec_csr_any_unq_d = any_csr_d & i0_valid_d;

		output logic [31:0] dec_pmp_rddata_d, // pmp CSR read data
		output logic dec_pmp_read_d, // pmp CSR address match

		output el2_pmp_cfg_pkt_t pmp_pmpcfg [pt.PMP_ENTRIES],
		output logic [31:0] pmp_pmpaddr [pt.PMP_ENTRIES],

		logic [pt.PMP_ENTRIES-1:0] entry_lock_eff; // Effective entry lock
		for (genvar r = 0; r < pt.PMP_ENTRIES; r++) begin : g_pmpcfg_lock

		// Smepmp allow modifying locked entries when mseccfg.RLB is set
		assign entry_lock_eff[r] = pmp_pmpcfg[r].lock & ~mseccfg.RLB;

User mode support #187

User mode support #187

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