PandABrick target

apps/PandABrick.app.ini

@@ -0,0 +1,12 @@
+[.]
+description:
+    Standard set of PandABlocks with:
+        - built-in FMC encoder card
+        - PandA synchroniser on SFP on-board FMC
+target: PandABrick
+includes: common_soft_blocks.include.ini
+
+[SFP_SYNC]
+module: sfp_panda_sync
+ini: sfp_panda_sync_us.block.ini
+

common/hdl/defines/top_defines.vhd

@@ -28,9 +28,6 @@ subtype MOD_RANGE               is natural range 0 to MOD_COUNT-1;
 
 -- Read Addr to Ack delay
 constant RD_ADDR2ACK            : std_logic_vector(4 downto 0) := "00010";
-
--- Block instantiation numbers--------------------------------------------
-constant ENC_NUM                : natural := 4;
 --------------------------------------------------------------------------
 
 --------------------------------------------------------------------------
@@ -43,6 +40,7 @@ alias PBUSBW is top_defines_gen.PBUSBW;
 alias EBUSW is top_defines_gen.EBUSW;
 alias PCAP_STD_DEV_OPTION is top_defines_gen.PCAP_STD_DEV_OPTION;
 alias FINE_DELAY_OPTION is top_defines_gen.FINE_DELAY_OPTION;
+alias PICXO_OPTION is top_defines_gen.PICXO_OPTION;
 --------------------------------------------------------------------------
 
 constant DCARD_MONITOR          : std_logic_vector(2 downto 0) := "011";

common/hdl/encoders/encoders_top.vhd

@@ -9,6 +9,9 @@ use work.top_defines.all;
 use work.addr_defines.all;
 
 entity encoders_top is
+generic (
+    ENC_NUM : natural
+);
 port (
     -- Clock and Reset
     clk_i                   : in  std_logic;

common/python/generate_app.py

@@ -36,7 +36,8 @@
 # ini file
 FPGA_OPTIONS_DEFAULTS = {
     'pcap_std_dev': False,
-    'fine_delay': False
+    'fine_delay': False,
+    'PICXO' : False,
 }
 
 

ip_defs/sfp_panda_sync_us.tcl

@@ -0,0 +1,31 @@
+#
+# Create SFP sync mgt core for Ultrascale+
+create_ip -vlnv [get_ipdefs -filter {NAME == gtwizard_ultrascale}] \
+-module_name sfp_panda_sync_us -dir $BUILD_DIR/
+
+set_property -dict [list \
+  CONFIG.DISABLE_LOC_XDC {true} \
+  CONFIG.CHANNEL_ENABLE {X0Y5} \
+  CONFIG.LOCATE_RX_USER_CLOCKING {CORE} \
+  CONFIG.LOCATE_TX_USER_CLOCKING {CORE} \
+  CONFIG.RX_COMMA_ALIGN_WORD {4} \
+  CONFIG.RX_COMMA_M_ENABLE {true} \
+  CONFIG.RX_COMMA_PRESET {K28.5} \
+  CONFIG.RX_COMMA_P_ENABLE {true} \
+  CONFIG.RX_COMMA_SHOW_REALIGN_ENABLE {false} \
+  CONFIG.RX_COMMA_VALID_ONLY {0} \
+  CONFIG.RX_DATA_DECODING {8B10B} \
+  CONFIG.RX_LINE_RATE {5} \
+  CONFIG.RX_MASTER_CHANNEL {X0Y5} \
+  CONFIG.RX_PLL_TYPE {CPLL} \
+  CONFIG.RX_REFCLK_FREQUENCY {125} \
+  CONFIG.RX_REFCLK_SOURCE {X0Y5 clk1} \
+  CONFIG.TX_DATA_ENCODING {8B10B} \
+  CONFIG.TX_LINE_RATE {5} \
+  CONFIG.TX_MASTER_CHANNEL {X0Y5} \
+  CONFIG.TX_PLL_TYPE {CPLL} \
+  CONFIG.TX_REFCLK_FREQUENCY {125} \
+  CONFIG.TX_REFCLK_SOURCE {X0Y5 clk1} \
+] [get_ips sfp_panda_sync_us]
+
+

modules/pandabrick_test/hdl/test_regs.vhd

@@ -0,0 +1,70 @@
+----------------------------------------------------------------------------------
+-- Dummy Module - replaced SYSTEM with this which returns test_val 
+----------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.top_defines.all;
+use work.addr_defines.all;
+
+
+entity test_regs is
+    Port ( 
+
+        clk_i         : in  std_logic;
+
+        test_val      : in std_logic_vector (31 downto 0);
+
+        -- Internal read interface
+        read_strobe   : in  std_logic;
+        read_address  : in  std_logic_vector(PAGE_AW-1 downto 0);
+        read_data     : out std_logic_vector(31 downto 0);
+        read_ack      : out std_logic;
+
+        -- Internal write interface
+        write_strobe  : in  std_logic;
+        write_address : in  std_logic_vector(PAGE_AW-1 downto 0);
+        write_data    : in  std_logic_vector(31 downto 0);
+        write_ack     : out std_logic
+
+	);
+end test_regs;
+
+architecture arch_test_regs of test_regs is
+
+signal test_address  :  std_logic_vector(PAGE_AW-1 downto 0);
+
+begin
+
+read_ack  <= '1';
+write_ack <= '1';
+
+process (clk_i) is
+begin
+    if rising_edge(clk_i) then
+
+        -- Start by creating a full set of 'zero's
+        --for index in 0 to (MOD_COUNT-1) loop
+        --    read_data(index) <= (others => '0');
+        --end loop;
+
+        -- Check for 'SYSTEM' module address
+        if (read_strobe='1') then
+            -- Check for address=0.
+            test_address <= (others => '0');
+            if (read_address = test_address) then
+                read_data <= test_val;
+            else
+                read_data <= (others => '0');
+            end if;
+        end if;
+
+    end if;
+end process;
+
+
+
+end arch_test_regs;

modules/pandabrick_test/pandabrick_test.block.ini

@@ -0,0 +1,8 @@
+[.]
+description: Test block for PandABrick
+entity: test_regs
+
+[TEST_VAL]
+type: read int
+description: Test Value
+