Merge pull request #164 from PandABlocks/sync_fixes

Various PandA-sync fixes

apps/PandABox-fmc_lback-sfp_lback.app.ini

@@ -5,6 +5,7 @@ description:
         - loopback SPF modules in all 3 sites
     Used for hardware testing only
 target: PandABox
+options: fine_delay
 includes: common_soft_blocks.include.ini
 
 [FMC_LBACK]

apps/PandABox-no-fmc-sfp1_dls_eventr.app.ini → apps/PandABox-no-fmc-sfp3_dls_eventr.app.ini

@@ -2,18 +2,18 @@
 description:
     Standard set of PandABox blocks with:
         - no FMC modules
-        - DLS event reciever on SFP1
-        - PandA synchroniser on SFP3
+        - DLS event reciever on SFP3
+        - PandA synchroniser on SFP2
 target: PandABox
 options: !pcap_std_dev
 includes: common_soft_blocks.include.ini
 
-[SFP1_EVR]
+[SFP3_EVR]
 module: sfp_eventr
 ini: sfp_dls_eventr.block.ini
-site: sfp 1
+site: sfp 3
 
-[SFP3_SYNC]
+[SFP2_SYNC]
 module: sfp_panda_sync
-site: sfp 3
+site: sfp 2
 

common/hdl/mmcm_clkmux.vhd

@@ -13,6 +13,7 @@ port (fclk_clk0_ps_i      : in  std_logic;
       sma_clk_i           : in  std_logic;
       mgt_rec_clk_i       : in  std_logic;
       clk_sel_i           : in  std_logic_vector(1 downto 0);
+      sfp_los_i           : in  std_logic;
       sma_pll_locked_o    : out std_logic;
       clk_sel_stat_o      : out std_logic_vector(1 downto 0);
       fclk_clk0_o         : out std_logic;
@@ -198,7 +199,7 @@ end generate;
 -- output from the secondary clock mux
 -- MUX sel checks only for lock from secondary (sma) PLL
 
-primary_mux_sel <= sma_pll_locked and (clk_sel_i(0) or clk_sel_i(1));
+primary_mux_sel <= sma_pll_locked and (clk_sel_i(0) or (clk_sel_i(1) and not sfp_los_i));
 
 clk_mux_bufh: BUFH
     port map (
@@ -208,7 +209,7 @@ clk_mux_bufh: BUFH
 
 -- Assign outputs
 
-clk_sel_stat_o <= (1 => clk_sel_i(1) and sma_pll_locked, 0 => clk_sel_i(0) and sma_pll_locked);
+clk_sel_stat_o <= "00" when primary_mux_sel = '0' else "01" when clk_sel_i(1) = '0' else "10";
 fclk_clk0_o <= fclk_clk_buf;
 fclk_clk0_2x_o <= fclk_clk_2x_buf;
 sma_pll_locked_o <= sma_pll_locked;

modules/sfp_eventr/hdl/sfp_event_receiver.vhd

@@ -3,6 +3,7 @@ use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
 use work.picxo_pkg.all;
+use work.support.all;
 
 library unisim;
 use unisim.vcomponents.all;
@@ -131,6 +132,8 @@ component event_receiver_mgt
 
 end component;
 
+constant DELAY_3ms : natural := 375_000; -- 3 ms at 125 MHz
+
 signal gt0_rxoutclk                 : std_logic;
 signal gt0_txoutclk                 : std_logic;
 signal rxoutclk                     : std_logic;
@@ -156,6 +159,8 @@ signal GT0_TX_FSM_RESET_DONE_sync   : std_logic;
 signal GT0_RX_FSM_RESET_DONE_sync   : std_logic;
 signal gt0_txresetdone_sync         : std_logic;
 signal gt0_rxresetdone_sync         : std_logic;
+signal init_rst                     : std_logic;
+signal mgt_rst                      : std_logic;
 
 -- PICXO control parameters (currently default to constant init values in pkg)
 signal  G1                              : STD_LOGIC_VECTOR (4 downto 0)     := c_G1;
@@ -174,12 +179,12 @@ signal  hold                            : std_logic                         := c
 signal  acc_step                        : STD_LOGIC_VECTOR (3 downto 0)     := c_acc_step;
 
 -- PICXO Monitoring signals (currently dangling, but can be connected to ILA)
-signal error_o                          : STD_LOGIC_VECTOR (20 downto 0) ;
-signal volt_o                           : STD_LOGIC_VECTOR (21 downto 0) ;
-signal drpdata_short_o                  : STD_LOGIC_VECTOR (7  downto 0) ;
-signal ce_pi_o                          : STD_LOGIC ;
-signal ce_pi2_o                         : STD_LOGIC ;
-signal ce_dsp_o                         : STD_LOGIC ;
+signal picxo_error                          : STD_LOGIC_VECTOR (20 downto 0) ;
+signal volt                           : STD_LOGIC_VECTOR (21 downto 0) ;
+signal drpdata_short                  : STD_LOGIC_VECTOR (7  downto 0) ;
+signal ce_pi                          : STD_LOGIC ;
+signal ce_pi2                         : STD_LOGIC ;
+signal ce_dsp                         : STD_LOGIC ;
 signal ovf_pd                           : STD_LOGIC ;
 signal ovf_ab                           : STD_LOGIC ;
 signal ovf_volt                         : STD_LOGIC ;
@@ -191,7 +196,6 @@ attribute equivalent_register_removal   : string;
 attribute shreg_extract of picxo_rst                  : signal is "no";
 attribute equivalent_register_removal of picxo_rst    : signal is "no"; 
 
-
 begin
 
 -- Assign outputs
@@ -263,12 +267,29 @@ data_valid <= '1';
 gt0_qplloutclk_in <= '0';
 gt0_qplloutrefclk_in <= '0';
 
+-- Hold MGT in reset for 3 ms after startup
+-- See Xilinx AR#65199
+startup_rst: process(sysclk_i)
+  variable startup_ctr : unsigned(LOG2(DELAY_3ms) downto 0) := (others => '0');
+begin
+    if rising_edge(sysclk_i) then
+        if startup_ctr = DELAY_3ms then
+            init_rst <= '0';
+        else
+            init_rst <= '1';
+            startup_ctr := startup_ctr + 1;
+        end if;
+    end if;
+end process;
+
+mgt_rst <= event_reset_i or init_rst;
+
 event_receiver_mgt_inst : event_receiver_mgt
     port map
         (
         SYSCLK_IN                   => GTREFCLK,
-        SOFT_RESET_TX_IN            => event_reset_i,
-        SOFT_RESET_RX_IN            => event_reset_i,
+        SOFT_RESET_TX_IN            => mgt_rst,
+        SOFT_RESET_RX_IN            => mgt_rst,
         DONT_RESET_ON_DATA_ERROR_IN => '0',
         GT0_TX_FSM_RESET_DONE_OUT   => GT0_TX_FSM_RESET_DONE,
         GT0_RX_FSM_RESET_DONE_OUT   => GT0_RX_FSM_RESET_DONE,
@@ -405,12 +426,12 @@ sfp_eventr_PICXO : PICXO_FRACXO
         DRPBUSY_O => open,
 
         ACC_DATA => open,
-        ERROR_O => error_o,
-        VOLT_O => volt_o,
-        DRPDATA_SHORT_O => drpdata_short_o,
-        CE_PI_O => ce_pi_o,
-        CE_PI2_O => ce_pi2_o,
-        CE_DSP_O => ce_dsp_o,
+        ERROR_O => picxo_error,
+        VOLT_O => volt,
+        DRPDATA_SHORT_O => drpdata_short,
+        CE_PI_O => ce_pi,
+        CE_PI2_O => ce_pi2,
+        CE_DSP_O => ce_dsp,
         OVF_PD => ovf_pd,
         OVF_AB => ovf_ab,
         OVF_VOLT => ovf_volt,