Merge pull request #162 from PandABlocks/reg_read_fix

Remove over-riding of ctrl block ack ports where feasible

common/hdl/encoders/encoders_top.vhd

@@ -68,24 +68,26 @@ signal OUTENC_read_strobe       : std_logic_vector(ENC_NUM-1 downto 0);
 signal OUTENC_read_data         : std32_array(ENC_NUM-1 downto 0);
 signal OUTENC_write_strobe      : std_logic_vector(ENC_NUM-1 downto 0);
 signal OUTENC_read_ack          : std_logic_vector(ENC_NUM-1 downto 0);
+signal OUTENC_write_ack         : std_logic_vector(ENC_NUM-1 downto 0);
 
 signal INENC_read_strobe        : std_logic_vector(ENC_NUM-1 downto 0);
 signal INENC_read_data          : std32_array(ENC_NUM-1 downto 0);
 signal INENC_write_strobe       : std_logic_vector(ENC_NUM-1 downto 0);
 signal posn                     : std32_array(ENC_NUM-1 downto 0);
 signal INENC_read_ack           : std_logic_vector(ENC_NUM-1 downto 0);
+signal INENC_write_ack          : std_logic_vector(ENC_NUM-1 downto 0);
 
 begin
 
 -- Acknowledgement to AXI Lite interface
-OUTENC_write_ack_o <= '1';
+OUTENC_write_ack_o <= or_reduce(OUTENC_write_ack);
 OUTENC_read_ack_o <= or_reduce(OUTENC_read_ack);
 
 -- Multiplex read data out from multiple instantiations
 OUTENC_read_data_o <= OUTENC_read_data(to_integer(unsigned(read_address_i(PAGE_AW-1 downto BLK_AW))));
 
 -- Acknowledgement to AXI Lite interface
-INENC_write_ack_o <= '1';
+INENC_write_ack_o <= or_reduce(INENC_write_ack);
 INENC_read_ack_o <= or_reduce(INENC_read_ack);
 
 -- Multiplex read data out from multiple instantiations
@@ -118,14 +120,14 @@ port map (
     OUTENC_read_ack_o       => OUTENC_read_ack(I),
 
     OUTENC_write_strobe_i   => OUTENC_write_strobe(I),
-    OUTENC_write_ack_o      => open,
+    OUTENC_write_ack_o      => OUTENC_write_ack(I),
 
     INENC_read_strobe_i     => INENC_read_strobe(I),
     INENC_read_data_o       => INENC_read_data(I),
     INENC_read_ack_o        => INENC_read_ack(I),
 
     INENC_write_strobe_i    => INENC_write_strobe(I),
-    INENC_write_ack_o       => open,
+    INENC_write_ack_o       => INENC_write_ack(I),
 
     read_address_i          => read_address_i(BLK_AW-1 downto 0),
 

common/templates/block_ctrl.vhd.jinja2

@@ -77,6 +77,8 @@ begin
         DELAY_i       => RD_ADDR2ACK
     );
 
+    write_ack_o <= '1';
+
     -- Control System Register Interface
     REG_WRITE : process(clk_i)
     begin

common/templates/block_wrapper.vhd.jinja2

@@ -80,11 +80,12 @@ signal write_strobe     : std_logic_vector(NUM-1 downto 0);
 signal read_addr        : natural range 0 to (2**read_address_i'length - 1);
 signal write_addr       : natural range 0 to (2**write_address_i'length - 1);
 signal read_ack         : std_logic_vector(NUM-1 downto 0);
+signal write_ack        : std_logic_vector(NUM-1 downto 0);
 
 begin
 
     -- Acknowledgement to AXI Lite interface
-    write_ack_o <= '1';
+    write_ack_o <= or_reduce(write_ack);
     read_ack_o <= or_reduce(read_ack);
     read_data_o <= read_data(to_integer(unsigned(read_address_i(PAGE_AW-1 downto BLK_AW))));
 
@@ -126,7 +127,7 @@ begin
             write_strobe_i      => write_strobe(I),
             write_address_i     => write_address_i(BLK_AW-1 downto 0),
             write_data_i        => write_data_i,
-            write_ack_o         => open
+            write_ack_o         => write_ack(I)
         );
 
         -- Connect to the actual logic entity

modules/fmc_24vio/hdl/fmc_24vio_wrapper.vhd

@@ -49,7 +49,7 @@ port (
     write_strobe_i      : in  std_logic;
     write_address_i     : in  std_logic_vector(PAGE_AW-1 downto 0);
     write_data_i        : in  std_logic_vector(31 downto 0);
-    write_ack_o         : out std_logic := '1';
+    write_ack_o         : out std_logic;
     FMC_i               : in  fmc_input_interface;
     FMC_io              : inout fmc_inout_interface := FMC_io_init
 );
@@ -75,18 +75,6 @@ signal fmc_out          : std_logic_vector(7 downto 0);
 
 begin
 
--- Acknowledgement to AXI Lite interface
-write_ack_o <= '1';
-
-read_ack_delay : entity work.delay_line
-generic map (DW => 1)
-port map (
-    clk_i       => clk_i,
-    data_i(0)   => read_strobe_i,
-    data_o(0)   => read_ack_o,
-    DELAY_i     => RD_ADDR2ACK
-);
-
 ---------------------------------------------------------------------------
 -- FMC CSR Interface
 ---------------------------------------------------------------------------
@@ -125,12 +113,12 @@ port map (
     read_strobe_i       => read_strobe_i,
     read_address_i      => read_address_i(BLK_AW-1 downto 0),
     read_data_o         => read_data_o,
-    read_ack_o          => open,
+    read_ack_o          => read_ack_o,
 
     write_strobe_i      => write_strobe_i,
     write_address_i     => write_address_i(BLK_AW-1 downto 0),
     write_data_i        => write_data_i,
-    write_ack_o         => open
+    write_ack_o         => write_ack_o
 );
 
 ---------------------------------------------------------------------------

modules/fmc_acq427/hdl/fmc_acq427_wrapper.vhd

@@ -49,7 +49,7 @@ port (
     write_strobe_i      : in  std_logic;
     write_address_i     : in  std_logic_vector(PAGE_AW-1 downto 0);
     write_data_i        : in  std_logic_vector(31 downto 0);
-    write_ack_o         : out std_logic := '1';
+    write_ack_o         : out std_logic;
     FMC_io              : inout fmc_inout_interface
 );
 end fmc_acq427_wrapper;
@@ -299,12 +299,12 @@ port map (
     read_strobe_i       => read_strobe_i,
     read_address_i      => read_address_i(BLK_AW-1 downto 0),
     read_data_o         => read_data_o,
-    read_ack_o          => open,
+    read_ack_o          => read_ack_o,
 
     write_strobe_i      => write_strobe_i,
     write_address_i     => write_address_i(BLK_AW-1 downto 0),
     write_data_i        => write_data_i,
-    write_ack_o         => open
+    write_ack_o         => write_ack_o
 );
 
 

modules/fmc_acq430/hdl/fmc_acq430_wrapper.vhd

@@ -121,10 +121,6 @@ attribute IOB       of s_ADC_SDO        : signal is "true";
 
 begin
 
--- Acknowledgement to AXI Lite interface
-write_ack_o <= '1';
-
-
 -- Control register interface
 -- Not actually used but added for consistency with other modules
 fmc_ctrl: entity work.fmc_acq430_ctrl
@@ -139,12 +135,12 @@ port map(
     read_strobe_i =>    read_strobe_i,
     read_address_i =>   read_address_i(BLK_AW-1 downto 0),
     read_data_o =>      read_data_o,
-    read_ack_o =>       open,
+    read_ack_o =>       read_ack_o,
 
     write_strobe_i =>   write_strobe_i,
     write_address_i =>  write_address_i(BLK_AW-1 downto 0),
     write_data_i =>     write_data_i,
-    write_ack_o =>      open
+    write_ack_o =>      write_ack_o
 );
 
 

modules/fmc_loopback/hdl/fmc_loopback_wrapper.vhd

@@ -104,18 +104,6 @@ port map (
     O => FMC_o.TXP_OUT
 );
 
--- Acknowledgement to AXI Lite interface
-write_ack_o <= '1';
-
-read_ack_delay : entity work.delay_line
-generic map (DW => 1)
-port map (
-    clk_i       => clk_i,
-    data_i(0)   => read_strobe_i,
-    data_o(0)   => read_ack_o,
-    DELAY_i     => RD_ADDR2ACK
-);
-
 -- Multiplex read data out from multiple instantiations
 
 -- Generate prescaled clock for internal counter
@@ -260,12 +248,12 @@ port map (
     read_strobe_i       => read_strobe_i,
     read_address_i      => read_address_i(BLK_AW-1 downto 0),
     read_data_o         => read_data_o,
-    read_ack_o          => open,
+    read_ack_o          => read_ack_o,
 
     write_strobe_i      => write_strobe_i,
     write_address_i     => write_address_i(BLK_AW-1 downto 0),
     write_data_i        => write_data_i,
-    write_ack_o         => open
+    write_ack_o         => write_ack_o
 );
 
 end rtl;

modules/lvdsout/hdl/lvdsout_top.vhd

@@ -50,10 +50,12 @@ signal read_strobe      : std_logic_vector(LVDSOUT_NUM-1 downto 0);
 signal read_data        : std32_array(LVDSOUT_NUM-1 downto 0);
 signal write_strobe     : std_logic_vector(LVDSOUT_NUM-1 downto 0);
 signal read_ack         : std_logic_vector(LVDSOUT_NUM-1 downto 0);
+signal write_ack        : std_logic_vector(LVDSOUT_NUM-1 downto 0);
+
 begin
 
 -- Acknowledgement to AXI Lite interface
-write_ack_o <= '1';
+write_ack_o <= or_reduce(write_ack);
 read_ack_o <= or_reduce(read_ack);
 
 --
@@ -80,7 +82,7 @@ port map (
     write_strobe_i      => write_strobe(I),
     write_address_i     => write_address_i(BLK_AW-1 downto 0),
     write_data_i        => write_data_i,
-    write_ack_o         => open,
+    write_ack_o         => write_ack(I),
     -- Block inputs
     bit_bus_i           => bit_bus_i,
     -- Block outputs

modules/pcap/hdl/pcap_core_ctrl.vhd

@@ -63,6 +63,18 @@ signal read_address     : natural range 0 to (2**read_address_i'length - 1);
 
 begin
 
+-- Acknowledgement to AXI Lite interface
+write_ack_o <= '1';
+
+read_ack_delay : entity work.delay_line
+generic map (DW => 1)
+port map (
+    clk_i       => clk_i,
+    data_i(0)   => read_strobe_i(DRV_CS),
+    data_o(0)   => read_ack_o,
+    DELAY_i     => RD_ADDR2ACK
+);
+
 -- Integer conversion for address.
 read_address <= to_integer(unsigned(read_address_i));
 write_address <= to_integer(unsigned(write_address_i));

modules/pcap/hdl/pcap_top.vhd

@@ -123,23 +123,6 @@ signal pos_bus_i_dyd    : pos_bus_t; -- pos_bus_i delayed
 
 begin
 
--- This module handles multiple register address spaces
--- Acknowledgement to AXI Lite interface
-write_ack_0_o <= '1';
-write_ack_1_o <= '1';
-
-
-read_ack_1 : entity work.delay_line
-generic map (DW => 1)
-port map (
-    clk_i       => clk_i,
-    data_i(0)   => read_strobe_i(DRV_CS),
-    data_o(0)   => read_ack_1_o,
-    DELAY_i     => RD_ADDR2ACK
-);
-
--- Multiplex read data out from multiple instantiations
-
 pcap_actv_o <= pcap_active;
 
 --------------------------------------------------------------------------
@@ -170,7 +153,7 @@ port map (
     write_strobe_i      => write_strobe_i(PCAP_CS),
     write_address_i     => write_address_i(BLK_AW-1 downto 0),
     write_data_i        => write_data_i,
-    write_ack_o         => open
+    write_ack_o         => write_ack_0_o
 );
 
 --------------------------------------------------------------------------
@@ -181,15 +164,15 @@ port map (
     clk_i               => clk_i,
     reset_i             => reset_i,
 
-    read_strobe_i       => (others => '0'),
+    read_strobe_i       => read_strobe_i,
     read_address_i      => read_address_i,
     read_data_o         => read_data_1_o,
-    read_ack_o          => open,
+    read_ack_o          => read_ack_1_o,
 
     write_strobe_i      => write_strobe_i,
     write_address_i     => write_address_i,
     write_data_i        => write_data_i,
-    write_ack_o         => open,
+    write_ack_o         => write_ack_1_o,
 
     START_WRITE         => START_WRITE,
     WRITE               => WRITE,

modules/sfp_eventr/hdl/sfp_dls_eventr_wrapper.vhd

@@ -31,7 +31,7 @@ port (
     write_strobe_i      : in  std_logic;
     write_address_i     : in  std_logic_vector(PAGE_AW-1 downto 0);
     write_data_i        : in  std_logic_vector(31 downto 0);
-    write_ack_o         : out std_logic := '1';
+    write_ack_o         : out std_logic;
 
     SFP_i               : in SFP_input_interface;
     SFP_o               : out SFP_output_interface
@@ -132,16 +132,6 @@ bit2_o(0) <= bit2;
 bit3_o(0) <= bit3;
 bit4_o(0) <= bit4;
 
-
-read_ack_delay : entity work.delay_line
-generic map (DW => 1)
-port map (
-    clk_i       => clk_i,
-    data_i(0)   => read_strobe_i,
-    data_o(0)   => read_ack_o,
-    DELAY_i     => RD_ADDR2ACK
-);
-
 sfp_transmitter_inst: entity work.sfp_transmitter
 port map(
      event_clk_i    => rxoutclk,
@@ -312,12 +302,12 @@ port map (
     read_strobe_i     => read_strobe_i,
     read_address_i    => read_address_i(BLK_AW-1 downto 0),
     read_data_o       => read_data_o,
-    read_ack_o        => open,
+    read_ack_o        => read_ack_o,
 
     write_strobe_i    => write_strobe_i,
     write_address_i   => write_address_i(BLK_AW-1 downto 0),
     write_data_i      => write_data_i,
-    write_ack_o       => open
+    write_ack_o       => write_ack_o
 );
 
 end rtl;

modules/sfp_loopback/hdl/sfp_loopback_wrapper.vhd

@@ -24,7 +24,7 @@ port (
     write_strobe_i      : in  std_logic;
     write_address_i     : in  std_logic_vector(PAGE_AW-1 downto 0);
     write_data_i        : in  std_logic_vector(31 downto 0);
-    write_ack_o         : out std_logic := '1';
+    write_ack_o         : out std_logic;
 
     -- SFP Interface
     SFP_i               : in SFP_input_interface;
@@ -60,15 +60,6 @@ port map (
     O => SFP_o.TXP_OUT
 );
 
-read_ack_delay : entity work.delay_line
-generic map (DW => 1)
-port map (
-    clk_i       => clk_i,
-    data_i(0)   => read_strobe_i,
-    data_o(0)   => read_ack_o,
-    DELAY_i     => RD_ADDR2ACK
-);
-
 --
 -- 2./ GTX Loopback Test
 --
@@ -129,12 +120,12 @@ port map (
     read_strobe_i               => read_strobe_i,
     read_address_i              => read_address_i(BLK_AW-1 downto 0),
     read_data_o                 => read_data_o,
-    read_ack_o                  => open,
+    read_ack_o                  => read_ack_o,
 
     write_strobe_i              => write_strobe_i,
     write_address_i             => write_address_i(BLK_AW-1 downto 0),
     write_data_i                => write_data_i,
-    write_ack_o                 => open
+    write_ack_o                 => write_ack_o
 );
 
 end rtl;