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Add support for TI TMS570LC43 SoC #88741

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@ntavish ntavish commented Apr 17, 2025

The SoC has a Cortex-R5 CPU, it required big-endian and BE32 compiler flags. I enabled big-endian ARMv7-R in the SDK toolchain here, and maybe only this CPU uses it as of now: zephyrproject-rtos/sdk-ng#765

I only have (and plan to use) only this specific SoC (TMS570LC43xx), so I focus on getting this chip working, but variants should be able to utilize this code mostly as is (AFAIK).

There is some code in the soc directory (soc.c, asm_funcs.S, soc_pll_errata.c) that is adapted from "TI Halcogen" generated code. It was license BSD 3-clause, and I am checking with TI support if they could help re-licensing it, so I did not create an RFC for the board related to that yet. I did not want to add this to the HAL module, as I am exporting only very limited portions of what the Halcogen generates, but open to suggestions.

Comment on lines 177 to 183
config PLATFORM_SPECIFIC_PRE_STACK_INIT
bool "Platform (SOC) specific startup hook executed before the stack is initialised"
help
The platform specific initialization code (z_arm_platform_pre_stack_init) is
executed in the early startup code right after the registers are set to known
values and before stack is set up. Note that this code cannot use the stack unlike
z_arm_platform_init.
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@nashif for review

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decided to not include this commit, soc_reset_hook is sufficient with a small fix before jumping to z_prep_c.

Comment on lines 23 to 46
clocks {
/*
* OSC_IN (16 MHZ)
* -> PLL1 (300 MHz)
* -> GCLK1 (300 MHz)
* -> HCLK (150 MHz)
* -> VCLK (75 MHz)
* -> RTICLK (75 MHz, divider is bypassed when VCLK is the source)
*/
};
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why is this an empty section with no nodes?

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@nordicjm thak you for the review, I have fixed the PR based on your comments. Sorry it was still in draft, I was rebasing and refactoring some code still from an older branch. I will still keep it in draft for today, while I add some description, and also try to figure out what to do with the BSD 3-clause code from TI.

bool

config SOC_FAMILY
default "ti_hercules" if SOC_FAMILY_HERCULES
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names must match either: default "hercules" if SOC_FAMILY_HERCULES or default "ti_hercules" if SOC_FAMILY_TI_HERCULES, soc.yml must also match

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fixed

Comment on lines 5 to 14
# TMS470 requires the ARM "legacy Word Invariant Addressing big-endian mode"
zephyr_compile_options(
-mbe32
${TOOLCHAIN_C_FLAGS}
)

zephyr_ld_options(
-mbe32
${TOOLCHAIN_LD_FLAGS}
)
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@tejlmand for comment


# launchpad is 16MHz
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 16000000
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needs to come from dts property

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Fixed the comment and value, but kept it in Kconfig.defconfig as several other SoCs seem to have it too.

Comment on lines 1 to 3
# SPDX-License-Identifier: Apache-2.0
CONFIG_PINCTRL=y
CONFIG_PINCTRL_TI_TMS570=y
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no

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fixed

default y
depends on DT_HAS_TI_TMS570_VIM_ENABLED
help
The TI Vectored Interrupt Manager provides hardware assistance for prioritizing
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help indent is 1x tab followed by 2x spaces

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fixed

if CPU_CORTEX_R5

config TMS570_VIM
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how does this relate to cortex r5 if it's a ti specific thing?

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fixed

Comment on lines 81 to 113

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fix in original commit

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fixed, I think

Comment on lines 37 to 38
config FLASH_BASE_ADDRESS
default 1000000
default 0x00000000
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fix in original commit

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fixed

@ntavish ntavish force-pushed the feature/add-tms570lc43 branch from 6fb7d8e to 338a715 Compare April 24, 2025 04:45
@ntavish ntavish changed the title Feature/add tms570lc43 Add support for TI TMS570LC43 SoC Apr 24, 2025
@ntavish ntavish force-pushed the feature/add-tms570lc43 branch 6 times, most recently from c5325f3 to cc4599b Compare April 24, 2025 12:23
@ntavish ntavish marked this pull request as ready for review April 25, 2025 04:02
@github-actions github-actions bot added area: Testsuite Testsuite area: Pinctrl area: UART Universal Asynchronous Receiver-Transmitter area: GPIO platform: TI SimpleLink Texas Instruments SimpleLink MCU area: Interrupt Controller area: Timer Timer area: ARM ARM (32-bit) Architecture labels Apr 25, 2025
@github-actions github-actions bot requested a review from wearyzen April 25, 2025 04:03
@ntavish ntavish force-pushed the feature/add-tms570lc43 branch from d5d6978 to f058209 Compare April 25, 2025 04:03
@@ -0,0 +1,334 @@
/* SPDX-License-Identifier: BSD-3-Clause */
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We typically cannot have BSD-3-Clause licensed code in the tree, as this needs to be approved by the governing board (see https://docs.zephyrproject.org/latest/contribute/guidelines.html#components-using-other-licenses).

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I sent a message to TI support regarding this, but I am not sure. If it doesn't go anywhere in 1 week, I will create a PR for hal_ti, and re-arrange this PR a bit.

@henrikbrixandersen henrikbrixandersen added the Licensing The PR has licensing issues => licensing expert to review label Apr 25, 2025
@@ -174,6 +174,14 @@ config PLATFORM_SPECIFIC_INIT

This option is deprecated, use SOC_RESET_HOOK instead.

config PLATFORM_SPECIFIC_PRE_STACK_INIT
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z_arm_platform_init was deprecated so a new config shouldn't be created taking it as a reference. You could add SOC_PRE_STACK_RESET_HOOK or something here but I would request to add an explanation why a pre stack soc init is needed in commit message and help section.

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I removed this commit and made use of soc_reset_hook after adding a small fix.

Tavish Naruka added 8 commits June 2, 2025 16:02
Functions called prior to z_prep_c might not preserve r4 which
was loaded earlier on before setting up the stacks. This commit
explicitly loads the address of z_prep_c to r4 before using it
for a branch.

Signed-off-by: Tavish Naruka <[email protected]>
Adds new SoC. The vendor provides a tool (halcogen) to
generate code including SoC init and errata handling code, which
is also included here after adapting it to coding style and reducing
dependencies. As for erratas, the applicable one at this stage is PLL
startup errata.

We also have CORTEX-R5#7 (ARM ID-780125), but we did not implement it
due to several reasons:
1. did not implement it in the past codebase
2. Halcogen code does not implement it
3. This is Cortex R5 errata, Xilinx R5 implementation has this note
https://adaptivesupport.amd.com/s/article/65878

Signed-off-by: Tavish Naruka <[email protected]>
Adds driver for TI TMS570 SoC.

Signed-off-by: Tavish Naruka <[email protected]>
Adds SCI peripheral UART driver for TMS570.

Signed-off-by: Tavish Naruka <[email protected]>
Add TI VIM driver specific to the TMS570 chips. This driver/peripheral
is not compatible with the existing intc_vim.c for some other TI chips.

Signed-off-by: Tavish Naruka <[email protected]>
Adds the RTI timer for TI TMS570 SoC and enables it as the system timer
for enabling multithreading.

Signed-off-by: Tavish Naruka <[email protected]>
Adds TI TMS570 SoC GPIO driver.

Signed-off-by: Tavish Naruka <[email protected]>
Adds minimal config for TI TMS570 launchpad which has the
TMS570LC43 SoC.

Signed-off-by: Tavish Naruka <[email protected]>
@ntavish ntavish force-pushed the feature/add-tms570lc43 branch from f058209 to bf845a8 Compare June 3, 2025 05:55
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area: ARM ARM (32-bit) Architecture area: GPIO area: Interrupt Controller area: Pinctrl area: Testsuite Testsuite area: Timer Timer area: UART Universal Asynchronous Receiver-Transmitter Licensing The PR has licensing issues => licensing expert to review platform: TI SimpleLink Texas Instruments SimpleLink MCU
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5 participants