boards: amd: Add support for AMD Versal NET RPU

boards/amd/versalnet_rpu/Kconfig.versalnet_rpu

@@ -0,0 +1,8 @@
+#
+# Copyright (c) 2025 Advanced Micro Devices, Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config BOARD_VERSALNET_RPU
+	select SOC_AMD_VERSALNET_RPU

boards/amd/versalnet_rpu/board.cmake

@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2025 Advanced Micro Devices, Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+include(${ZEPHYR_BASE}/boards/common/xsdb.board.cmake)

boards/amd/versalnet_rpu/board.yml

@@ -0,0 +1,5 @@
+board:
+  name: versalnet_rpu
+  vendor: amd
+  socs:
+  - name: amd_versalnet_rpu

boards/amd/versalnet_rpu/support/xsdb.cfg

@@ -0,0 +1,44 @@
+# Copyright (c) 2025 Advanced Micro Devices, Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+proc load_image args  {
+	set elf_file [lindex $args 0]
+
+	if { [info exists ::env(HW_SERVER_URL)] } {
+		connect -url $::env(HW_SERVER_URL)
+	} else {
+		connect
+	}
+
+	after 100
+	targets -set -nocase -filter {name =~ "Versal*"}
+	after 100
+	rst -system
+	after 100
+
+	if { [info exists ::env(PDI_FILE_PATH)] } {
+		device program $::env(PDI_FILE_PATH)
+	} else {
+		puts "Error: env variable PDI_FILE_PATH is not set"
+		exit
+	}
+
+	after 100
+	targets -set -nocase -filter {name =~ "DPC"}
+	after 100
+	# Configure timestamp generator to run global timer gracefully
+	# Ideally these registers should be set from bootloader (cdo)
+	mwr -force 0xeb5b0000 0x1
+	mwr -force 0xeb5b0020 100000000
+	after 100
+
+	targets -set -nocase -filter {name =~ "*Cortex-R52 #0.0"}
+	rst -proc
+	after 100
+	dow -force $elf_file
+	con
+	exit
+}
+
+load_image {*}$argv

boards/amd/versalnet_rpu/versalnet_rpu.dts

@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2025, Advanced Micro Devices, Inc.
+ *
+ * Mubin Sayyed <[email protected]>
+ */
+
+/dts-v1/;
+#include <arm/xilinx/versalnet_r52.dtsi>
+
+/ {
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,ocm = &ocm;
+	};
+};
+
+&cpu0 {
+	 clock-frequency = <100000000>;
+};
+
+&soc {
+	sram0: memory@0 {
+		compatible = "mmio-sram";
+		reg = <0x00000 DT_SIZE_M(2048)>;
+	};
+};
+
+&ocm {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+	current-speed = <115200>;
+	clock-frequency = <100000000>;
+};
+
+&uart0 {
+	status = "okay";
+	current-speed = <115200>;
+	clock-frequency = <100000000>;
+};

boards/amd/versalnet_rpu/versalnet_rpu.yaml

@@ -0,0 +1,10 @@
+identifier: versalnet_rpu
+name: AMD Development board for Versal NET RPU
+arch: arm
+toolchain:
+  - zephyr
+testing:
+  ignore_tags:
+    - net
+    - bluetooth
+vendor: amd

boards/amd/versalnet_rpu/versalnet_rpu_defconfig

@@ -0,0 +1,9 @@
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable serial port
+CONFIG_UART_PL011=y

dts/arm/xilinx/versalnet_r52.dtsi

@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2025, Advanced Micro Devices, Inc.
+ *
+ * Mubin Sayyed <[email protected]>
+ */
+
+/dts-v1/;
+
+#include <mem.h>
+#include <arm/armv8-r.dtsi>
+#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
+#include <amd/versalnet.dtsi>
+
+/ {
+	model = "Versal NET RPU";
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-r52";
+			reg = <0>;
+		};
+	};
+
+	arch_timer: timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&gic>;
+		status = "okay";
+	};
+};
+
+&soc {
+	interrupt-parent = <&gic>;
+
+	gic: interrupt-controller@e2000000 {
+		compatible = "arm,gic-v3", "arm,gic";
+		reg = <0xe2000000 0x10000>,
+					<0xe2100000 0x80000>;
+		interrupt-controller;
+		#interrupt-cells = <4>;
+		status = "okay";
+	};
+};

dts/common/amd/versalnet.dtsi

@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2025, Advanced Micro Devices, Inc.
+ *
+ * Mubin Sayyed <[email protected]>
+ */
+
+/ {
+	soc: soc {
+		ocm: memory@bbf00000 {
+			compatible = "zephyr,memory-region";
+			reg = <0xbbf00000 DT_SIZE_M(1)>;
+			status = "disabled";
+			zephyr,memory-region = "OCM";
+		};
+
+		uart0: uart@f1920000 {
+			compatible = "arm,sbsa-uart";
+			reg = <0xf1920000 0x4c>;
+			status = "disabled";
+			interrupt-names = "irq_0";
+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		};
+
+		uart1: uart@f1930000 {
+			compatible = "arm,sbsa-uart";
+			reg = <0xf1930000 0x1000>;
+			status = "disabled";
+			interrupt-names = "irq_1";
+			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		};
+	};
+};

soc/xlnx/versalnet/CMakeLists.txt

@@ -0,0 +1,19 @@
+#
+# Copyright (c) 2025 Advanced Micro Devices, Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_sources(
+  soc.c
+)
+zephyr_sources_ifdef(
+  CONFIG_ARM_MPU
+  arm_mpu_regions.c
+)
+
+zephyr_include_directories(.)
+
+if(CONFIG_SOC_AMD_VERSALNET_RPU)
+  set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "")
+endif()

soc/xlnx/versalnet/Kconfig

@@ -0,0 +1,15 @@
+#
+# Copyright (c) 2025 Advanced Micro Devices, Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config SOC_AMD_VERSALNET_RPU
+	select ARM
+	select ARM_ARCH_TIMER
+	select CPU_CORTEX_R52
+	select SOC_EARLY_INIT_HOOK
+	select CPU_HAS_DCLS
+	select GIC_SINGLE_SECURITY_STATE
+	select CPU_HAS_ARM_MPU
+	select ARM_MPU

soc/xlnx/versalnet/Kconfig.defconfig

@@ -0,0 +1,22 @@
+#
+# Copyright (c) 2025 Advanced Micro Devices, Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_AMD_VERSALNET
+
+if SOC_AMD_VERSALNET_RPU
+
+CONFIG_CACHE_MANAGEMENT=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_CACHE_MANAGEMENT=y
+
+config NUM_IRQS
+	# must be >= the highest interrupt number used
+	# - include the UART interrupts
+	default 256
+
+endif # SOC_AMD_VERSALNET_RPU
+
+endif # SOC_AMD_VERSALNET

soc/xlnx/versalnet/Kconfig.soc

@@ -0,0 +1,23 @@
+#
+# Copyright (c) 2025 Advanced Micro Devices, Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config SOC_AMD_VERSALNET
+	bool
+
+config SOC_AMD_VERSALNET_RPU
+	bool
+	select SOC_AMD_VERSALNET
+	help
+	  AMD Versal NET SoC
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
+
+config SOC_FAMILY
+	default "amd_versalnet" if SOC_AMD_VERSALNET
+
+config SOC
+	default "amd_versalnet_rpu" if SOC_AMD_VERSALNET_RPU

soc/xlnx/versalnet/arm_mpu_regions.c

@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2025 Advanced Micro Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/linker/linker-defs.h>
+#include <zephyr/arch/arm/mpu/arm_mpu.h>
+
+#define DEVICE_REGION_START	0xE2000000U
+#define DEVICE_REGION_END	0xF8000000U
+
+static const struct arm_mpu_region mpu_regions[] = {
+	MPU_REGION_ENTRY("vector",
+			 (uintptr_t)_vector_start,
+			 REGION_RAM_TEXT_ATTR((uintptr_t)_vector_end)),
+
+	MPU_REGION_ENTRY("SRAM_TEXT",
+			 (uintptr_t)__text_region_start,
+			 REGION_RAM_TEXT_ATTR((uintptr_t)__rodata_region_start)),
+
+	MPU_REGION_ENTRY("SRAM_RODATA",
+			 (uintptr_t)__rodata_region_start,
+			 REGION_RAM_RO_ATTR((uintptr_t)__rodata_region_end)),
+
+	MPU_REGION_ENTRY("SRAM_DATA",
+			 (uintptr_t)__rom_region_end,
+			 REGION_RAM_ATTR((uintptr_t)__kernel_ram_end)),
+
+	MPU_REGION_ENTRY("DEVICE",
+			 DEVICE_REGION_START,
+			 REGION_DEVICE_ATTR(DEVICE_REGION_END)),
+};
+
+const struct arm_mpu_config mpu_config = {
+	.num_regions = ARRAY_SIZE(mpu_regions),
+	.mpu_regions = mpu_regions,
+};

soc/xlnx/versalnet/soc.c

@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2025 Advanced Micro Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/cache.h>
+#include <zephyr/device.h>
+#include <zephyr/kernel.h>
+
+void soc_early_init_hook(void)
+{
+	if (IS_ENABLED(CONFIG_ICACHE)) {
+		if (!(__get_SCTLR() & SCTLR_I_Msk)) {
+			L1C_InvalidateICacheAll();
+			__set_SCTLR(__get_SCTLR() | SCTLR_I_Msk);
+			barrier_isync_fence_full();
+		}
+	}
+
+	if (IS_ENABLED(CONFIG_DCACHE)) {
+		if (!(__get_SCTLR() & SCTLR_C_Msk)) {
+			L1C_InvalidateDCacheAll();
+			__set_SCTLR(__get_SCTLR() | SCTLR_C_Msk);
+			barrier_dsync_fence_full();
+		}
+	}
+}

soc/xlnx/versalnet/soc.h

@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2025 Advanced Micro Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _SOC_XLNX_VERSALNET_SOC_H_
+#define _SOC_XLNX_VERSALNET_SOC_H_
+
+/* Define CMSIS configurations */
+#define __GIC_PRESENT 0
+#define __TIM_PRESENT 0
+
+#endif /* _SOC_XLNX_VERSALNET_SOC_H_ */

soc/xlnx/versalnet/soc.yml

@@ -0,0 +1,4 @@
+family:
+- name: amd_versalnet
+  socs:
+  - name: amd_versalnet_rpu