boards: amd: Add support for AMD Versal NET RPU #86276
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| CONFIG_ARM_MPU=y | ||
| CONFIG_CACHE_MANAGEMENT=y | ||
| CONFIG_DCACHE=y | ||
| CONFIG_ICACHE=y |
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why can't these be set by soc?
| CONFIG_ISR_STACK_SIZE=1024 | ||
| CONFIG_THREAD_STACK_INFO=y | ||
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| CONFIG_ARM_MPU=y | ||
| CONFIG_CACHE_MANAGEMENT=y | ||
| CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=100000000 |
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why can't this be set at soc level?
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=100000000 - this is configurable based on HW design and not really hardcoded in SOC.
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will read it from dt parameter
dts/arm/xilinx/versalnet_r52.dtsi
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| interrupt-parent = <&gic>; | ||
| status = "okay"; | ||
| }; | ||
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dts/arm/xilinx/versalnet_r52.dtsi
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| #interrupt-cells = <4>; | ||
| status = "okay"; | ||
| }; | ||
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soc/xlnx/versalnet/Kconfig.soc
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| default "amd_versalnet" if SOC_AMD_VERSALNET | ||
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| config SOC | ||
| default "versalnet_rpu" if SOC_AMD_VERSALNET_RPU |
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name mismatch either needs to be default "amd_versalnet_rpu" if SOC_AMD_VERSALNET_RPU or default "versalnet_rpu" if SOC_VERSALNET_RPU, and soc.yml needs to be the same
| CONFIG_DCACHE=y | ||
| CONFIG_ICACHE=y |
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These items are already provided for any Cortex-R52 CPU in arch/arm/core/cortex_a_r/Kconfig.
| # SPDX-License-Identifier: Apache-2.0 | ||
| # | ||
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| config SOC_AMD_VERSALNET_RPU |
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add 'select ARM_MPU' here , then you can remove the other instances of 'CONFIG_ARM_MPU=y'.
soc/xlnx/versalnet/soc.c
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| #include <zephyr/device.h> | ||
| #include <zephyr/kernel.h> | ||
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| void z_arm_platform_init(void) |
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In order for z_arm_platform_init() to be executed, you'll have to select PLATFORM_SPECIFIC_INIT. However, this is deprecated and therefore shouldn't be used. You can do things like disabling the caches, adjusting VBAR if available, or making sure that HIVECS is cleared at the earliest stages of booting in soc_reset_hook() which goes into soc.c. With this current implementation of z_arm_platform_init(), the caches are enabled before the MPU is set up.
Have a look at #85537 as reference, this PR is currently in progress, adding cache support for the Cortex-R5.
Thanks for the review, will fix |
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Add support for the RPU, real-time processing unit on Versal NET SoC. It is based on Cortext-R52 processor. The patch contains initial wiring and configuration for generic board with OCM(1MB) and DDR(2G) memories, cpu, interrupt controller, global timer and UART. versalnet.dtsi contains common peripherals integrated into Versal NET SoC, and versalnet_r52.dtsi has peripherals which are private to Cortex-R52 processor. Signed-off-by: Mubin Sayyed <[email protected]> Signed-off-by: Appana Durga Kedareswara rao <[email protected]>
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Add generic board support for the RPU, real-time processing unit on Versal NET SoC. It is based on Cortext-R52 processor. Signed-off-by: Mubin Sayyed <[email protected]> Signed-off-by: Appana Durga Kedareswara rao <[email protected]>
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Add support for the RPU, real-time processing unit on Versal NET SoC. It is based on Cortext-R52 processor.
The patch contains initial wiring and configuration for generic board with OCM(1MB) and DDR(2G) memories, cpu, interrupt controller, global timer and UART.
versalnet.dtsi contains common peripherals integrated into Versal NET SoC, and versalnet_r52.dtsi has peripherals which are private to Cortex-R52 processor.
CC: @mubinsyed