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stm32cube: h7rsxx : sync stm32h7rsxx with the correct h7rs cube repo history #273

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stm32cube: h7rsxx : sync stm32h7rsxx with the correct h7rs cube repo history #273

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8c1d89f
stm32cube: stm32h7rsxx: soc: update h7 soc files
djiatsaf-st Apr 17, 2025
32aebe5
stm32cube: stm32h7rsxx: drivers: include: update hal-ll header
djiatsaf-st Apr 17, 2025
41b00fd
stm32cube: stm32h7rsxx: drivers: src: update hal-ll src driver
djiatsaf-st Apr 17, 2025
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14 changes: 12 additions & 2 deletions stm32cube/stm32h7rsxx/drivers/include/Legacy/stm32_hal_legacy.h
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Expand Up @@ -554,6 +554,16 @@ extern "C" {
#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE
#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE
#endif /* STM32U5 */
#if defined(STM32U0)
#define OB_USER_nRST_STOP OB_USER_NRST_STOP
#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL
#define OB_USER_nBOOT0 OB_USER_NBOOT0
#define OB_USER_nBOOT1 OB_USER_NBOOT1
#define OB_nBOOT0_RESET OB_NBOOT0_RESET
#define OB_nBOOT0_SET OB_NBOOT0_SET
#endif /* STM32U0 */

/**
* @}
Expand Down Expand Up @@ -3792,10 +3802,10 @@ extern "C" {
#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1

#if !defined(STM32U0)
#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1

#endif

#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
Expand Down
2 changes: 1 addition & 1 deletion stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_cortex.h
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Expand Up @@ -388,7 +388,7 @@ void HAL_CORTEX_ClearEvent(void);

#define IS_MPU_SUB_REGION_DISABLE(__SUBREGION__) ((__SUBREGION__) < (uint16_t)0x00FFU)

#define IS_MPU_ADDRESS_MULTIPLE_SIZE(__ADDRESS__, __SIZE__) (((__ADDRESS__) & (1<<(__SIZE__+1U))- 1U) == 0U)
#define IS_MPU_ADDRESS_MULTIPLE_SIZE(__ADDRESS__, __SIZE__) (((__ADDRESS__) & ((1<<(__SIZE__+1U))- 1U)) == 0U)

/**
* @}
Expand Down
4 changes: 4 additions & 0 deletions stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_def.h
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Expand Up @@ -130,6 +130,10 @@ typedef enum
/* Macro to get buffer 32-bytes aligned (aligned to cache line width) */
#define ALIGN_32BYTES(buf) buf __attribute__((aligned(32)))

/* Macro to get buffer 8-bytes aligned (aligned to double-word width) */
/* This alignment is required for double-word DMA transfers */
#define ALIGN_8BYTES(buf) buf __attribute__((aligned(8)))

/* Legacy macros to get variable 4-bytes aligned */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
Expand Down
4 changes: 2 additions & 2 deletions stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_flash_ex.h
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Expand Up @@ -204,8 +204,8 @@ void HAL_FLASHEx_EnableEccDetectionInterrupt(void);
void HAL_FLASHEx_DisableEccDetectionInterrupt(void);
void HAL_FLASHEx_GetEccInfo(FLASH_EccInfoTypeDef *pData);
void HAL_FLASHEx_ECCD_IRQHandler(void);
__weak void HAL_FLASHEx_EccDetectionCallback(void);
__weak void HAL_FLASHEx_EccCorrectionCallback(void);
void HAL_FLASHEx_EccDetectionCallback(void);
void HAL_FLASHEx_EccCorrectionCallback(void);
/**
* @}
*/
Expand Down
2 changes: 1 addition & 1 deletion stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_mdios.h
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Expand Up @@ -83,7 +83,7 @@ typedef struct
typedef struct __MDIOS_HandleTypeDef
#else
typedef struct
#endif
#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
{
MDIOS_TypeDef *Instance; /*!< Register base address */

Expand Down
4 changes: 0 additions & 4 deletions stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_rcc.h
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Expand Up @@ -4103,7 +4103,6 @@ typedef struct
* 192 to 836 MHz or 128 to 560 MHz(*) if PLL2VCOSEL = 0
* 150 to 420 MHz if PLL2VCOSEL = 1.
*
* (*) : For stm32h7a3xx and stm32h7b3xx family lines.
*
* @retval None
*/
Expand All @@ -4129,7 +4128,6 @@ typedef struct
* @arg RCC_PLL_VCO_HIGH: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*)
* @arg RCC_PLL_VCO_LOW: Range frequency is between 150 and 420 MHz
*
* (*) : For stm32h7a3xx and stm32h7b3xx family lines.
*
* @retval None
*/
Expand Down Expand Up @@ -4242,7 +4240,6 @@ typedef struct
* 192 to 836 MHz or 128 to 560 MHz(*) if PLL3VCOSEL = 0
* 150 to 420 MHz if PLL3VCOSEL = 1.
*
* (*) : For stm32h7a3xx and stm32h7b3xx family lines.
*
* @retval None
*/
Expand All @@ -4266,7 +4263,6 @@ typedef struct
* @arg RCC_PLL_VCO_HIGH: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*)
* @arg RCC_PLL_VCO_HIGH: Range frequency is between 150 and 420 MHz
*
* (*) : For stm32h7a3xx and stm32h7b3xx family lines.
*
* @retval None
*/
Expand Down
6 changes: 3 additions & 3 deletions stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_rcc_ex.h
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Expand Up @@ -888,7 +888,7 @@ typedef struct
* @arg RCC_FMCCLKSOURCE_HCLK_DIV4 Recovery Clock selected as FMC clock
*/
#define __HAL_RCC_GET_FMC_SOURCE() ((READ_BIT(RCC->CKPROTR, RCC_CKPROTR_FMCSWP) == RCC_FMCCLKSOURCE_HCLK_DIV4) ? \
RCC_FMCCLKSOURCE_HCLK_DIV4 : ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_FMCSEL))))
RCC_FMCCLKSOURCE_HCLK_DIV4 : ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_FMCSEL))))

/** @brief Macro to configure the I2C1/I3C1 clock source.
* @param __I2C1_I3C1_CLKSOURCE__ specifies the I2C1/I3C1clock source.
Expand Down Expand Up @@ -1070,7 +1070,7 @@ typedef struct
* @arg RCC_XSPI1CLKSOURCE_HCLK_DIV4 Recovery Clock selected as XSPI1 clock
*/
#define __HAL_RCC_GET_XSPI1_SOURCE() ((READ_BIT(RCC->CKPROTR, RCC_CKPROTR_XSPI1SWP) == RCC_XSPI1CLKSOURCE_HCLK_DIV4) ? \
RCC_XSPI1CLKSOURCE_HCLK_DIV4 : ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_XSPI1SEL))))
RCC_XSPI1CLKSOURCE_HCLK_DIV4 : ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_XSPI1SEL))))

/** @brief Macro to configure the XSPI2 clock source.
*
Expand All @@ -1090,7 +1090,7 @@ typedef struct
* @arg RCC_XSPI2CLKSOURCE_HCLK_DIV4 Recovery Clock selected as XSPI2 clock
*/
#define __HAL_RCC_GET_XSPI2_SOURCE() ((READ_BIT(RCC->CKPROTR, RCC_CKPROTR_XSPI2SWP) == RCC_XSPI2CLKSOURCE_HCLK_DIV4) ? \
RCC_XSPI2CLKSOURCE_HCLK_DIV4 : ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_XSPI2SEL))))
RCC_XSPI2CLKSOURCE_HCLK_DIV4 : ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_XSPI2SEL))))

/**
* @brief Macro to configure the PSSI clock source.
Expand Down
39 changes: 20 additions & 19 deletions stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_rng_ex.h
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Expand Up @@ -34,19 +34,19 @@ extern "C" {
#if defined(RNG)
#if defined(RNG_CR_CONDRST)

/** @defgroup RNG_Ex RNG_Ex
/** @defgroup RNGEx RNGEx
* @brief RNG Extension HAL module driver
* @{
*/

/* Exported types ------------------------------------------------------------*/
/** @defgroup RNG_Ex_Exported_Types RNG_Ex Exported Types
* @brief RNG_Ex Exported types
/** @defgroup RNGEx_Exported_Types RNGEx Exported Types
* @brief RNGEx Exported types
* @{
*/

/**
* @brief RNG_Ex Configuration Structure definition
* @brief RNGEx Configuration Structure definition
*/

typedef struct
Expand All @@ -55,11 +55,11 @@ typedef struct
uint32_t Config2; /*!< Config2 must be a value between 0 and 0x7 */
uint32_t Config3; /*!< Config3 must be a value between 0 and 0xF */
uint32_t ClockDivider; /*!< Clock Divider factor.This parameter can
be a value of @ref RNG_Ex_Clock_Divider_Factor */
be a value of @ref RNGEx_Clock_Divider_Factor */
uint32_t NistCompliance; /*!< NIST compliance.This parameter can be a
value of @ref RNG_Ex_NIST_Compliance */
value of @ref RNGEx_NIST_Compliance */
uint32_t AutoReset; /*!< automatic reset When a noise source error occurs
value of @ref RNG_Ex_Auto_Reset */
value of @ref RNGEx_Auto_Reset */
uint32_t HealthTest; /*!< RNG health test control must be a value
between 0x0FFCABFF and 0x00005200 */
} RNG_ConfigTypeDef;
Expand All @@ -69,11 +69,11 @@ typedef struct
*/

/* Exported constants --------------------------------------------------------*/
/** @defgroup RNG_Ex_Exported_Constants RNG_Ex Exported Constants
/** @defgroup RNGEx_Exported_Constants RNGEx Exported Constants
* @{
*/

/** @defgroup RNG_Ex_Clock_Divider_Factor Value used to configure an internal
/** @defgroup RNGEx_Clock_Divider_Factor Value used to configure an internal
* programmable divider acting on the incoming RNG clock
* @{
*/
Expand Down Expand Up @@ -112,7 +112,7 @@ typedef struct
* @}
*/

/** @defgroup RNG_Ex_NIST_Compliance NIST Compliance configuration
/** @defgroup RNGEx_NIST_Compliance NIST Compliance configuration
* @{
*/
#define RNG_NIST_COMPLIANT (0x00000000UL) /*!< NIST compliant configuration*/
Expand All @@ -121,7 +121,7 @@ typedef struct
/**
* @}
*/
/** @defgroup RNG_Ex_Auto_Reset Auto Reset configuration
/** @defgroup RNGEx_Auto_Reset Auto Reset configuration
* @{
*/
#define RNG_ARDIS_ENABLE (0x00000000UL) /*!< automatic reset after seed error*/
Expand All @@ -136,7 +136,7 @@ typedef struct
*/

/* Private types -------------------------------------------------------------*/
/** @defgroup RNG_Ex_Private_Types RNG_Ex Private Types
/** @defgroup RNGEx_Private_Types RNGEx Private Types
* @{
*/

Expand All @@ -145,7 +145,7 @@ typedef struct
*/

/* Private variables ---------------------------------------------------------*/
/** @defgroup RNG_Ex_Private_Variables RNG_Ex Private Variables
/** @defgroup RNGEx_Private_Variables RNGEx Private Variables
* @{
*/

Expand All @@ -154,7 +154,7 @@ typedef struct
*/

/* Private constants ---------------------------------------------------------*/
/** @defgroup RNG_Ex_Private_Constants RNG_Ex Private Constants
/** @defgroup RNGEx_Private_Constants RNGEx Private Constants
* @{
*/

Expand All @@ -163,7 +163,7 @@ typedef struct
*/

/* Private macros ------------------------------------------------------------*/
/** @defgroup RNG_Ex_Private_Macros RNG_Ex Private Macros
/** @defgroup RNGEx_Private_Macros RNGEx Private Macros
* @{
*/

Expand Down Expand Up @@ -202,7 +202,7 @@ typedef struct
*/

/* Private functions ---------------------------------------------------------*/
/** @defgroup RNG_Ex_Private_Functions RNG_Ex Private Functions
/** @defgroup RNGEx_Private_Functions RNGEx Private Functions
* @{
*/

Expand All @@ -211,11 +211,11 @@ typedef struct
*/

/* Exported functions --------------------------------------------------------*/
/** @addtogroup RNG_Ex_Exported_Functions
/** @addtogroup RNGEx_Exported_Functions
* @{
*/

/** @addtogroup RNG_Ex_Exported_Functions_Group1
/** @addtogroup RNGEx_Exported_Functions_Group1
* @{
*/
HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigTypeDef *pConf);
Expand All @@ -226,7 +226,7 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng);
* @}
*/

/** @addtogroup RNG_Ex_Exported_Functions_Group2
/** @addtogroup RNGEx_Exported_Functions_Group2
* @{
*/
HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng);
Expand Down Expand Up @@ -260,3 +260,4 @@ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng);


#endif /* STM32H7RSxx_HAL_RNG_EX_H */

15 changes: 9 additions & 6 deletions stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_sdio.h
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Expand Up @@ -434,19 +434,21 @@ HAL_StatusTypeDef HAL_SDIO_GetCardFBRRegister(SDIO_HandleTypeDef *hsdio, HAL_SDI
/** @defgroup SDIO_Exported_Functions_Group3 Process functions
* @{
*/
HAL_StatusTypeDef HAL_SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_DirectCmd_TypeDef *Argument, uint8_t *pData);
HAL_StatusTypeDef HAL_SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_DirectCmd_TypeDef *Argument, uint8_t Data);
HAL_StatusTypeDef HAL_SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_DirectCmd_TypeDef *Argument,
uint8_t *pData);
HAL_StatusTypeDef HAL_SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_DirectCmd_TypeDef *Argument,
uint8_t Data);

HAL_StatusTypeDef HAL_SDIO_ReadExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument,
HAL_StatusTypeDef HAL_SDIO_ReadExtended(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_ExtendedCmd_TypeDef *Argument,
uint8_t *pData, uint32_t Size_byte, uint32_t Timeout_Ms);

HAL_StatusTypeDef HAL_SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument,
HAL_StatusTypeDef HAL_SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_ExtendedCmd_TypeDef *Argument,
uint8_t *pData, uint32_t Size_byte, uint32_t Timeout_Ms);

HAL_StatusTypeDef HAL_SDIO_ReadExtended_DMA(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument,
HAL_StatusTypeDef HAL_SDIO_ReadExtended_DMA(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_ExtendedCmd_TypeDef *Argument,
uint8_t *pData, uint32_t Size_byte);

HAL_StatusTypeDef HAL_SDIO_WriteExtended_DMA(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument,
HAL_StatusTypeDef HAL_SDIO_WriteExtended_DMA(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_ExtendedCmd_TypeDef *Argument,
uint8_t *pData, uint32_t Size_byte);
/**
* @}
Expand Down Expand Up @@ -598,3 +600,4 @@ HAL_StatusTypeDef HAL_SDIO_DisableIOAsynInterrupt(SDIO_HandleTypeDef *hsdio);


#endif /* STM32H7RSxx_HAL_SDIO_H */

1 change: 1 addition & 0 deletions stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_usart_ex.h
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Expand Up @@ -279,3 +279,4 @@ HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, ui
#endif

#endif /* STM32H7RSxx_HAL_USART_EX_H */

8 changes: 4 additions & 4 deletions stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_ll_dlyb.h
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Expand Up @@ -31,8 +31,8 @@ extern "C" {
* @{
*/

#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_OSPI_MODULE_ENABLED) || defined(HAL_XSPI_MODULE_ENABLED)
#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2) || defined (DLYB_OCTOSPI1) || defined (DLYB_OCTOSPI2)
#if defined(HAL_SD_MODULE_ENABLED)
#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2)

/* Exported types ------------------------------------------------------------*/
/** @defgroup DLYB_LL DLYB
Expand Down Expand Up @@ -129,8 +129,8 @@ uint32_t LL_DLYB_GetClockPeriod(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_c
* @}
*/

#endif /* DLYB_SDMMC1 || DLYB_SDMMC2 || DLYB_OCTOSPI1 || DLYB_OCTOSPI2 */
#endif /* HAL_SD_MODULE_ENABLED || HAL_OSPI_MODULE_ENABLED || HAL_XSPI_MODULE_ENABLED */
#endif /* DLYB_SDMMC1 || DLYB_SDMMC2 */
#endif /* HAL_SD_MODULE_ENABLED */

/**
* @}
Expand Down
4 changes: 2 additions & 2 deletions stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_ll_rcc.h
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Expand Up @@ -75,7 +75,7 @@ extern "C" {
*/
#if !defined(UNUSED)
#define UNUSED(x) ((void)(x))
#endif
#endif /* UNUSED */

#define LL_CLKSOURCE_SHIFT(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_POS_SHIFT ) & 0x1FUL)

Expand Down Expand Up @@ -5445,7 +5445,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
}

/**
* @brief Check if RCC flag Low Power D1 reset is set or not.
* @brief Check if RCC flag Low Power reset is set or not.
* @rmtoll RSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
* @retval State of bit (1 or 0).
*/
Expand Down
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